Abstract: A plurality of pins couple the cones and the shift collar of a transmission auxiliary section together so that they rotate as a group. When the shift collar is moved laterally from neutral, the shift collar engages blocking surfaces on the pins and moves the corresponding cone to match the speeds of the input shaft and the corresponding gear. The invention shortens the pin lengths of the synchronizer and therefore the length of the transmission, by eliminating contact between the shift collar and the small diameters of the pins in the neutral position.

Abstract: A plurality of pins couple the cones and the shift collar of a transmission auxiliary section together so that they rotate as a group. When the shift collar is moved laterally from neutral, the shift collar engages blocking surfaces on the pins and moves the corresponding cone to match the speeds of the input shaft and the corresponding gear. The invention shortens the pin lengths of the synchronizer and therefore the length of the transmission, by eliminating contact between the shift collar and the small diameters of the pins in the neutral position.

Abstract: An improved synchronizer uses a friction element to induce a frictional torque to rotating gear and collar elements. The rotational speeds of the gear and collar elements are electronically monitored by a transmission control unit. When the transmission control unit has determined that the rotational speeds of the gear and the collar are equalized, another control drives the collar to engage the gear.

Abstract: A plurality of pins couple the cones and the shift collar of a transmission auxiliary section together so that they rotate as a group. When the shift collar is moved laterally from neutral, the shift collar engages blocking surfaces on the pins and moves the corresponding cone to match the speeds of the input shaft and the corresponding gear. The invention shortens the pin lengths of the synchronizer and therefore the length of the transmission, by eliminating contact between the shift collar and the small diameters of the pins in the neutral position.

Abstract: A vehicle transmission assembly includes a main gear box and an auxiliary gear box assembly, such as a range gear box. The range gearbox is shifted by an Electric Over Air (EOA) system that includes an air supply, a controller and a single solenoid. The solenoid valve is selectively operated by the controller which includes a timer function. When the driver actuates the range switch, the solenoid valve is energized for a predetermined period of time until the shift has been accomplished. Upon completion of the shift, the controller deenergizes the solenoid valve which then returns to a neutral condition.

Abstract: A vehicle transmission assembly includes a main gear box that supports an auxiliary gear box assembly, such as a range gear box. The main gear box has a shaft that is coupled to a shaft of the range gear box assembly. The range gear box assembly includes selectively engageable range gears, a shifting assembly, and a range piston assembly. The range piston assembly includes a single piece housing, an air filter regulator, and a range position sensor. The sensor monitors range selection of the range gears and produces a range position signal that is sent to an electronic control unit. The air regulator is threadably attached to the single piece housing and provides air to a pneumatic piston that resides in the housing. The pneumatic piston is used to control the positioning of the range gears.

Abstract: A multispeed transmission includes a range section having a plural cone synchronizer. The plural cone synchronizer is utilized to assist in transmitting the high torque load typically found in low range. The inventive synchronizer includes a unique structure for selectively connecting the outer and inner cones.

Abstract: Structures for saving states of memory cells in an FPGA while the FPGA is being configured are shown. Structures for saving flip flop states, lookup table configurations, and block RAM states are specifically described. Structures are described having (1) a SAVE STATE bit for saving the state of each flip flop, each lookup table RAM, and each block RAM. With these structures, each storage unit can be selectively restored. (2) a SAVE STATE bit for each row(column) of logic blocks in the FPGA. In such structures it is possible with a single SAVE STATE signal to selectively save or restore every memory element in the row, possibly including flip flops, lookup tables, and blocks of RAM. Several structures and methods for providing the SAVE STATE signal are also described.

Abstract: The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention.