Abstract: A size M×N sparse matrix, including zero values, is multiplied with a size N vector, using a processor arrangement. A data storage linked to the processor arrangement stores the matrix in a compressed formal. Zero values are not stored. The data storage stores the vector as vector parts, each of a respective size Ki, 1<Ki<N and i=1 . . . P. A vector part comprises a vector element in common with another vector part. Each vector part is stored in a distinct memory block. Each of a plurality of the non-zero values of a matrix row is associated with a memory block storing an element of the vector having an index corresponding with a respective index of the non-zero value. The processor arrangement multiplies, in parallel, each of the plurality of the non-zero values of the matrix row by the respective vector element having a corresponding index stored in the associated memory block.

Abstract: A size M×N sparse matrix, including zero values, is multiplied with a size N vector, using a processor arrangement. A data storage linked to the processor arrangement stores the matrix in a compressed formal. Zero values are not stored. The data storage stores the vector as vector parts, each of a respective size Ki, 1<Ki<N and i=1 . . . P. A vector part comprises a vector element in common with another vector part. Each vector part is stored in a distinct memory block. Each of a plurality of the non-zero values of a matrix row is associated with a memory block storing an element of the vector having an index corresponding with a respective index of the non-zero value. The processor arrangement multiplies, in parallel, each of the plurality of the non-zero values of the matrix row by the respective vector element having a corresponding index stored in the associated memory block.