Abstract: Techniques for generating a digital wardrobe are presented herein. A transceiver can be configured to receive a request having a garment identifier and a user identifier. Additionally, an access module can be configured to access a first garment model, access a body model of the user corresponding to the user identifier, and access a second garment model corresponding to the user identifier. Furthermore, a processor can be configured by a garment simulation module to position the body model inside the first garment model and the second garment model, and calculate simulated forces based on the positioning. Moreover, a rendering module can be configured to generate an image of the garment models draped on the body model based on the calculated simulated forces. Subsequently, a display module can be configured to cause presentation of the generated image on a display of a device.

Abstract: Techniques for mapping size information associated with a client to target brands, garments, sizes, shapes, and styles for which there is no standardized correlation. The size information associated with a client may be generated by modeling client garments, accessing computer aided drawing (CAD) files associated with client garments, or by analyzing a history of garment purchases associated with the client. Information for target garments may be generated in a similar fashion. A system may then create a standardized scale with a set of sizes for a target, and map a client base size to that standardized size scale. Similar matching and mapping may also be done with shape and style considerations. A recommendation based on the mapping may then be communicated to the client.

Abstract: A method for using a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor. For each of the read requests, a determination is made as to whether there is a cache line hit corresponding to the request. For each cache line miss, a cache line slot is allocated to store a new cache line responsive to the cache line miss. An in-order set of cache lines is output to the video processor responsive to the queue of read requests.

Abstract: Systems and methods for regional item recommendations are provided. In example embodiments, an indication of a destination geolocation from a user device of a user is received. Destination data corresponding to the destination geolocation is retrieved. A destination characteristic from the destination data is extracted. The destination characteristic indicates an affinity for apparel associated with the destination geolocation. A candidate apparel item is determined based on the extracted destination characteristic. An item listing corresponding to the candidate apparel item is identified. The item listing is presented on a user interface of the user device.

Abstract: Techniques for an omni-channel approach for displaying simulated digital apparel content are presented herein. A machine can detect an available amount of a computing resource on a client device. A determination that the client device is to render only a three-dimensional body model, among a set of models that includes the three-dimensional body model and a three-dimensional garment model, and that a server is to render the three-dimensional garment model, may occur based on the detected available amount of the computing resource on the client device. The machine can provide the client device with the three-dimensional garment model draped on the three-dimensional body model. The machine can cause the server to render at least a portion of the three-dimensional garment model in accordance with the determination. The machine can cause the client device to render at least a portion of the three-dimensional body model in accordance with the determination.

Abstract: Techniques for three-dimensional garment simulation using parallel computing are presented herein. An access module can be configured to access a three-dimensional garment model of a garment. The garment model can include garment points that represent a surface of the garment. A processor, having a plurality of cores, can be configured by a garment simulation module to calculate one or more exerted forces on a subset of garment points. Additionally, the garment simulation module can generate cross pairs and apportion the generated cross pairs among the plurality of cores. Moreover, the garment simulation module can determine, using the plurality of vector execution units in parallel based on an organized data layout, whether boundaries of the first subgroup of cross pairs are overlapping based on the one or more exerted forces. Subsequently, the garment simulation module can calculate one or more simulated forces acting on the garment points based on the determination.

Abstract: Techniques for three-dimensional garment simulation are presented herein. An access module can be configured to access a three-dimensional garment model of a garment. The garment model can include garment points that represent a surface of the garment. Additionally, a three-dimensional body model can be generated based on body measurements, body scanning, or garment information. A processor can be configured by a garment module to position at least a portion of the generated three-dimensional body model inside the garment points, and calculate one or more simulated forces acting on a subset of the garment points. Moreover, a rendering module can be configured to generate an image of the three-dimensional garment model draped on the three-dimensional body model based on the calculated one or more simulated forces. Furthermore, a display module can be configured to present the generated image on a display of a device.

Abstract: Techniques for generating and presenting a three-dimensional garment model are presented herein. A communication interface can be configured to receive images, where all visible parts of the garment may be captured by the received images. A garment creation module can be configured to generate partial shapes of the garment based on the received images. Additionally, the garment creation module can determine a type of garment by comparing the generated partial shapes to a database of reference garment shapes. Furthermore, the garment creation module can generate a three-dimensional garment model by joining the partial shapes based on the determined type of garment, and can tessellate the generated three-dimensional garment model. A user interface can be configured to present the tessellated three-dimensional garment model on a three-dimensional body model.

Abstract: Techniques for extraction of body parameters, dimensions and shape of a customer are presented herein. A model descriptive of a garment, a corresponding calibration factor and reference garment shapes can be assessed. A garment shape corresponding to the three-dimensional model can be selected from the reference garment shapes based on a comparison of the three-dimensional model with the reference garment shapes. A reference feature from the plurality of reference features may be associated with the model feature. A measurement of the reference feature may be calculated based on the association and the calibration factor. The computed measurement can be stored in a body profile associated with a user. An avatar can be generated for the user based on the body profile and be used to show or indicate fit of a garment, as well as make fit and size recommendations.

Abstract: A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor, and tracking each of a plurality of cache lines stored within the cache using a least recently used variable. For each a cache line hit out of the plurality of cache lines and corresponding to one of the read requests, the least recently used variable is adjusted for a remainder of the plurality of cache lines. A replacement cache line is determined by examining the least recently used variables for each of the plurality of cache lines. For each cache line miss, a cache line slot corresponding to the replacement cache line is allocated to store a new cache line responsive to the cache line miss.

Abstract: A memory system, method, and computer program product are provided. In use, a plurality of portions of memory is arranged contiguously. Further, a number of requests required to retrieve the portions of memory is reduced utilizing the arrangement. In one possible embodiment, such technique may be used in the context of film grain technology (FGT), such that the portions of memory include portions of a film grain image stored in a film grain database (FGDB).

Abstract: An electrical rule check program takes simulation output files as input and performs an electrical rule check on the simulation to determine if any electrical design rules have been violated. The program scans a simulation output file to produce a subcircuit name list, an instance name list, and an internal index list for each subcircuit. If the number of circuit nodes is less than a first predetermined value, a window limit is set to equal the number of nodes times the number of data points. If the number of nodes is greater than the first predetermined value and less than a second predetermined value, then the window limit is set to equal some first predetermined fraction of the product of the number of nodes and the number of data points.

Abstract: The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

Abstract: A timing apparatus for monitoring when a memory array in a non-volatile storage device needs to be refreshed includes a programmable semiconductor device and detecting means for detecting when the amount of charge on the programmable semiconductor device has diminished to at most a threshold amount. In one embodiment, the programmable semiconductor device is a floating gate transistor programmed by adding charge to the floating gate. The detecting means monitors the I.sub.DS current of the transistor and determines an array refresh time when more than a negligible amount of I.sub.DS current is detected.

Abstract: An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals.