Abstract: An information processing apparatus and method for relighting captured images in a virtual reality environment is provided. Righting processing performed by the apparatus includes acquiring an input image, acquiring a target image, determining at least one shared reference region for the acquired input image and at least one shared reference region for the acquired target image, determining a transform matrix based on the color space of the shared region, applying the transform matrix to at least a portion of the acquired input image, outputting the transformed portion of the acquired input image, and displaying the outputted transformed portion of the acquired input image.

Abstract: A system for immersive virtual reality communication that includes a first capture device configured to capture a stream of images of a first user, a first network configured to transmit the captured stream of images of the first user, a second network configured to receive data based at least in part on the captured stream of images of the first user and a first virtual reality device used by a second user, wherein the first virtual reality device is configured to render a virtual environment and to produce a rendition of the first user based at least in part on the data based at least in part on the stream of images of the first user produced by the first capture device.

Abstract: Provided herein are anti-TSLP antibodies or antigen-binding fragments thereof, isolated poly nucleotides encoding the same, pharmaceutical compositions comprising the same, and the uses thereof.

Abstract: Techniques for routing communication to a common audio output device connected multiple audio signal source devices are disclosed. For each of audio signal source devices, a set of inputs are assessed. The set of inputs can include: an operational state of the audio signal source device, an interaction with the audio signal source device, an audio-producing application being executed by the audio signal source device, or a degree of user interaction with the audio-producing application. At a point in time, an audio routing score is generated for each of the audio signal source devices according to a weighted calculation of the set of inputs based on the assessing. Finally, an audio signal routing decision is made, to route an audio signal from one of the audio signal source devices to the audio output device, based on the audio routing score for each of the audio signal source devices.

Abstract: Techniques are described for reducing capacity fragmentation by using an Automatic Defragmentation Service (ADS). More particularly, hypervisors (HVs) that are candidates to defragment are identified, an HV to defragment is selected, and one or more VM instances are migrated from the selected HV to a different HV. According to certain implementations, instead of migrating a VM to a new HV, the VM is live migrated to an existing HV.

Abstract: An adenovirus or adenoviral vector is described that includes a non-native nucleotide sequence capable of expressing a chimeric protein comprising an N-terminal nucleotide binding domain of transactivation response element DNA-binding protein (TDP-43), a C-terminal domain derived from a splicing repressor, and an autoregulatory element. Methods of using the adenovirus or adenoviral vector to treat degenerative diseases such as inclusion body myocytosis, amyotrophic lateral sclerosis, and frontotemporal dementia are also described.

Abstract: A method of fabricating a spin-current switched magnetic memory element includes providing a wafer having a bottom electrode, forming a plurality of layers, such that interfaces between the plurality of layers are formed in situ, the plurality of layers includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers, lithographically defining a pillar structure from the plurality of layers, and forming a top electrode on the pillar structure.

Abstract: A method for fabricating a device includes forming a first insulation layer to cover a removable mask and a device structure that has been defined by the mask. The device structure is below the mask. The mask is lifted off to expose a top portion of the device structure. A conductive island structure is formed over the first insulation layer and the exposed top portion of the device structure. The first insulation layer and the conductive island structure are covered with a second insulation layer. A contact is formed through the second insulation layer to the conductive island structure.

Abstract: A method for fabricating a device includes forming a first insulation layer to cover a removable mask and a device structure that has been defined by the mask. The device structure is below the mask. The mask is lifted off to expose a top portion of the device structure. A conductive island structure is formed over the first insulation layer and the exposed top portion of the device structure. The first insulation layer and the conductive island structure are covered with a second insulation layer. A contact is formed through the second insulation layer to the conductive island structure.

Abstract: A method of tuning a high temperature superconductor (HTS) resonator includes the steps of providing a HTS inductor and a HTS capacitor, the HTS capacitor being electrically connected to the HTS inductor. A tuning body is provided adjacent to the HTS inductor and the HTS capacitor. The relative position of the tuning body with respect to the HTS inductor and the HTS capacitor is altered so as to tune the resonator. A tunable resonant circuit is provided that includes a substrate having a planar surface. At least one resonator formed from HTS material is disposed on the substrate, the resonator having one or more turns that when combined, turn through greater than 360°.

Abstract: A spin-current switchable magnetic memory element (and method of fabricating the memory element) includes a plurality of magnetic layers having a perpendicular magnetic anisotropy component, at least one of the plurality of magnetic layers including an alloy of a rare-earth metal and a transition metal, and at least one barrier layer formed adjacent to at least one of the plurality of magnetic layers.

Abstract: A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.

Abstract: A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.

Abstract: A spin-current switchable magnetic memory element (and method of fabricating the memory element) includes a plurality of magnetic layers having a perpendicular magnetic anisotropy component, at least one of the plurality of magnetic layers including an alloy of a rare-earth metal and a transition metal, and at least one barrier layer formed adjacent to at least one of the plurality of magnetic layers.

Abstract: A memory cell and method of fabricating the memory cell includes an insulating layer formed on a first electrode layer, the insulating layer having a first opening, a stencil layer formed on the insulating layer, and having a second opening formed in an area of the first opening, a phase-change material layer formed on a surface of the first electrode layer in the first opening, and an electrically conductive layer including a first portion formed on the stencil layer and defining a second electrode layer and a second portion formed on the phase-change material layer.

Abstract: A method of tuning a high temperature superconductor (HTS) resonator includes the steps of providing a HTS inductor and a HTS capacitor, the HTS capacitor being electrically connected to the HTS inductor. A tuning body is provided adjacent to the HTS inductor and the HTS capacitor. The relative position of the tuning body with respect to the HTS inductor and the HTS capacitor is altered so as to tune the resonator. A tunable resonant circuit is provided that includes a substrate having a planar surface. At least one resonator formed from HTS material is disposed on the substrate, the resonator having one or more turns that when combined, turn through greater than 360°.

Abstract: A memory cell and method of fabricating the memory cell includes an insulating layer formed on a first electrode layer, the insulating layer having a first opening, a stencil layer formed on the insulating layer, and having a second opening formed in an area of the first opening, a phase-change material layer formed on a surface of the first electrode layer in the first opening, and an electrically conductive layer including a first portion formed on the stencil layer and defining a second electrode layer and a second portion formed on the phase-change material layer.

Abstract: A magnetic memory element switchable by current injection includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers (e.g., between two of the magnetic layers). The memory element has the switching threshold current and device impedance suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuits.