Abstract: A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.

Abstract: An NMR system comprises an NMR probe comprising multiple NMR detection sites. Each of the multiple NMR detection sites comprises a sample holding void and an associated NMR microcoil. The NMR system further comprises a controllable fluid router operative to direct fluid sample to the multiple NMR detection sites.

Abstract: An NMR system comprises an NMR probe comprising multiple NMR detection sites. Each of the multiple NMR detection sites comprises a sample holding void and an associated NMR microcoil. The NMR system further comprises a controllable fluid router operative to direct fluid sample to the multiple NMR detection sites.

Abstract: An NMR system comprises an NMR probe comprising multiple NMR detection sites. Each of the multiple NMR detection sites comprises a sample holding void and an associated NMR microcoil. The NMR system further comprises a controllable fluid router operative to direct fluid sample to the multiple NMR detection sites.

Abstract: An NMR system comprises an NMR probe comprising multiple NMR detection sites. Each of the multiple NMR detection sites comprises a sample holding void and an associated NMR microcoil. The NMR system further comprises a controllable fluid router operative to direct fluid sample to the multiple NMR detection sites.

Abstract: A hardware logic arrangement for subtraction using a 3:2 carry-save-adder (CSA) for use with high speed floating point computation circuits. Three operands to be combined are routed to the three inputs of the CSA via separate multiplexors (MUXs) and appropriate inverting logic. Output sum and carry vectors are routed via further MUXs to separate latch storage registers. Subtraction executed as addition of the inverse of an operand is implemented by routing a constant "1" to the MUX steering the output carry vector to its associated latch.

Abstract: Apparatus for converting to a single precision or double precision number an extended precision floating point number comprised of a sign field, an exponent field and a mantissa field. A sticky generation logic connected to the mantissa bus calculates rounding bits for single and double precision and places the rounding information at a sticky output. Overflow and underflow detection logic connected to the exponent bus detects exponent overflow and underflow and generates an overflow output signal. Rounding and conversion control logic connected to the sticky output utilizes the type of conversion that has been specified and the rounding information at the sticky output for producing conversion controls at a control output and a conversion type signal output.