Patents by Inventor Jonathan Tsung-Yung Chang

Jonathan Tsung-Yung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210217446
    Abstract: A device disclosed includes first and second rows of memory cells, a first data line, and a first continuous data line. The first and second rows of memory cells are arranged in a first sub-bank and a second sub-bank, separated from the first sub-bank, respectively. The first data line is arranged across the first sub-bank and coupled to a first memory cell in the first row of memory cells. The first continuous data line includes a first portion arranged across the first sub-bank and a second portion arranged across the second sub-bank. The first continuous data line is coupled to a second memory cell in the second row of memory cells. The first portion of the first continuous data line is disposed in a first metal layer. The first data line and the second portion of the first continuous data line are in a second metal layer.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung CHANG, Cheng-Hung LEE, Chi-Ting CHENG, Hung-Jen LIAO, Jhon-Jhy LIAW, Yen-Huei CHEN
  • Publication number: 20210200452
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao HSU, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Hung-Jen LIAO, Jung-Ping YANG, Jonathan Tsung-Yung CHANG, Wei Min CHAN, Yen-Huei CHEN, Yangsyu LIN, Chien-Chen LIN
  • Patent number: 11031055
    Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Pankaj Aggarwal, Jhon Jhy Liaw
  • Patent number: 10991420
    Abstract: A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
  • Patent number: 10964355
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Publication number: 20210090621
    Abstract: A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 25, 2021
    Inventors: Shang-Chi WU, Yangsyu LIN, Chiting CHENG, Jonathan Tsung-Yung CHANG, Mahmut SINANGIL
  • Patent number: 10949100
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 16, 2021
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
  • Publication number: 20210050053
    Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 18, 2021
    Inventors: Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Yen-Ting Lin
  • Publication number: 20210043253
    Abstract: A circuit includes a memory array, a write circuit configured to store data in memory cells of the memory array, a read circuit configured to retrieve the stored data from the memory cells of the memory array, and a computation circuit configured to perform one or more logic operations on the retrieved stored data. The memory array is positioned between the write circuit and the read circuit.
    Type: Application
    Filed: October 22, 2020
    Publication date: February 11, 2021
    Inventors: Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Hidehiro FUJIWARA
  • Publication number: 20210043252
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Application
    Filed: October 12, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 10872659
    Abstract: A memory system includes a first array (of memory cells) and a second array (of write assist circuits) arranged into columns each including a bit line and a bit_bar line coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array, each write assist circuit including: latch and memory-adapted third and fourth NMOS transistors. The latch includes: memory-adapted first PMOS and first NMOS transistors connected in series between a power-supply voltage and a first node selectively connectable to a ground voltage; and memory-adapted second PMOS transistor and second NMOS transistors connected in series between the power-supply voltage and a second node selectively connectable to ground voltage. The third NMOS transistor is connected in series between the first node and ground voltage; and the fourth NMOS transistor connected in series between the second node and ground voltage.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yangsyu Lin, Chiting Cheng, Jonathan Tsung-Yung Chang, Shang-Chi Wu
  • Patent number: 10867646
    Abstract: A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chi Wu, Chiting Cheng, Jonathan Tsung-Yung Chang, Yangsyu Lin, Mahmut Sinangil
  • Patent number: 10854282
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Publication number: 20200372950
    Abstract: A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 26, 2020
    Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Li-Wen WANG, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN
  • Patent number: 10847214
    Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Yen-Ting Lin
  • Patent number: 10839894
    Abstract: A circuit includes a memory array, a write circuit configured to store data in memory cells of the memory array, a read circuit configured to retrieve the stored data from the memory cells of the memory array, and a computation circuit configured to perform one or more logic operations on the retrieved stored data. The memory array is positioned between the write circuit and the read circuit.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Huei Chen, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 10803928
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 10755768
    Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit; and a distributed write driving arrangement. The distributed write driving arrangement includes: a global write driver including a first inverter connected between the GWB line and the LWB line, and a second inverter connected between the GWB_bar line and the LWB_bar line; and a local write driver included at an interior of each segment, each local write driver including a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB_bar line and the LWB_bar line.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
  • Patent number: 10685686
    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
  • Publication number: 20200176037
    Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Inventors: Chien-Kuo SU, Cheng Hung LEE, Chiting CHENG, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN, Pankaj AGGARWAL, Jhon Jhy LIAW