Abstract: The disclosure is directed to a package for containing a plurality of substantially rectangular assay plates, each plate having a peripheral flange. In one embodiment, the package comprises a cavity having extending therein one or more sloped buttress elements spaced across at least a portion of a top corner, and one or more adjacent protrusions extending from the bottom and at least partially up one or both sidewalls, each set of protrusions forming grooves therebetween into which fit the flanges of respective assay plates. The package can comprise a transparent polymer through which product information located on the assay plates can be read or scanned.

Abstract: The disclosure is directed to a package for containing a plurality of substantially rectangular assay plates, each plate having a peripheral flange. In one embodiment, the package comprises a cavity having extending therein one or more sloped buttress elements spaced across at least a portion of a top corner, and one or more adjacent protrusions extending from the bottom and at least partially up one or both sidewalls, each set of protrusions forming grooves therebetween into which fit the flanges of respective assay plates. The package can comprise a transparent polymer through which product information located on the assay plates can be read or scanned.

Abstract: In some examples, a computing device can include a component device, a battery, and a memory resource storing instructions to cause a processing resource to determine an operating mode of the computing device, in response to the operating mode being a charging mode, cause the battery to charge, in response to the operating mode being a system battery mode, cause the battery to power the computing device, and in response to the operating mode being a battery reserve mode, cause the battery to power the component device in absence of powering other components of the computing device.

Abstract: In some examples, a system comprises: a socket; a controller coupled to the socket; a storage device comprising machine-readable instructions; and a processor coupled to the controller and the storage device, wherein execution of the machine-readable instructions causes the processor to: detect a Secure Digital (SD) card in the socket via the controller; prompt a user to select a communication protocol to be utilized by the system to communicate with the SD card; and enable the system to communicate with the SD card based on the user selection.

Abstract: The disclosure is directed to a package for containing a plurality of substantially rectangular assay plates, each plate having a peripheral flange. In one embodiment, the package comprises a cavity having extending therein one or more sloped buttress elements spaced across at least a portion of a top corner, and one or more adjacent protrusions extending from the bottom and at least partially up one or both sidewalls, each set of protrusions forming grooves therebetween into which fit the flanges of respective assay plates. The package can comprise a transparent polymer through which product information located on the assay plates can be read or scanned.

Abstract: The present disclosure provides generally for methods and systems relating to relocation estimates. According to the present disclosure, sales representatives and prospective customers may have access to the relocation estimate system to see how a quote is being generated and what the resource allocation was. These parties may make suggestions or ask questions about how a quote was generated. These parties may correct or update a quote based on needs not known during an initial walkthrough. Based on information input by a user, the relocation estimate system may provide a quote in real-time.

Abstract: In some examples, an adapter includes a COMPACTFLASH EXPRESS (CFX) connector interface to connect to a CFX connector of a computer, and a device connector interface to connect to any of a plurality of different devices comprising different types of interfaces. The device connector interface includes an indicator settable to any of a plurality of different states to represent a respective type of the different types of interfaces when a device is connected to the adapter, and the CFX connector interface comprising an indicator connected to the indicator of the device connector interface.

Abstract: The present disclosure provides generally for methods and systems relating to relocation management. More specifically, the methods and systems relate to monitoring and assessing the progress and status of a relocation. In some aspects, a move plan may be developed to perform a relocation, wherein the move plan may organize the logistics of the project. In some embodiments, a move plan may comprise move segments that may allow for more detailed logistics management and monitoring. In some implementations, a progress formula may be generated for a relocation based at least in part on the move plan, which may allow for a dynamic and accurate understanding of the progress and status of a relocation.

Abstract: In some examples, an adapter includes a COMPACTFLASH EXPRESS (CFX) connector interface to connect to a CFX connector of a computer, and a device connector interface to connect to any of a plurality of different devices comprising different types of interfaces. The device connector interface includes an indicator settable to any of a plurality of different states to represent a respective type of the different types of interfaces when a device is connected to the adapter, and the CFX connector interface comprising an indicator connected to the indicator of the device connector interface.

Abstract: Example implementations relate to memory power termination delays. In some examples, a computing system may include a memory storage device, a memory controller, an input/output (I/O) controller, a power management controller (PMC), a bus compliant with an Enhanced Serial Peripheral Interface (eSPI) protocol, and a power control gating. The input/output controller may transmit a power termination command to the power management controller via the bus compliant with the eSPI protocol. Upon a receipt of the power termination command, the PMC may initiate a delay period of an assertion of the power termination command to the power control gating and transmit a memory transfer command to the memory controller included in the memory storage device. The memory controller, upon receipt of the memory transfer command, may move data stored in volatile memory to non-volatile memory included in the memory storage device.

Abstract: A system may include a computing device. The computing device may include an optical disc drive (ODD) bay, wherein an ODD is not present in the ODD bay. The system may further include an ODD connector. The system may also include an external serial AT attachment (eSATA) device located in an opening of the ODD bay for housing the non-present ODD and coupled to the computing device by the ODD connector at the ODD bay.

Abstract: The present disclosure provides generally for methods and systems relating to relocation management. More specifically, the methods and systems relate to monitoring and assessing the progress and status of a relocation. In some aspects, a move plan may be developed to perform a relocation, wherein the move plan may organize the logistics of the project. In some embodiments, a move plan may comprise move segments that may allow for more detailed logistics management and monitoring. In some implementations, a progress formula may be generated for a relocation based at least in part on the move plan, which may allow for a dynamic and accurate understanding of the progress and status of a relocation.

Abstract: The present disclosure provides generally for methods and systems relating to relocation estimates. According to the present disclosure, sales representatives and prospective customers may have access to the relocation estimate system to see how a quote is being generated and what the resource allocation was. These parties may make suggestions or ask questions about how a quote was generated. These parties may correct or update a quote based on needs not known during an initial walkthrough. Based on information input by a user, the relocation estimate system may provide a quote in real-time.

Abstract: A comprehensive Memory-Resident Database Management System architecture and implementation is disclosed where a) all data storage in database is in memory, b) all database management functionality is in memory except backup and recovery storage based on hard disk, c) all database objects including tables, views, triggers, procedures, functions . . . are in memory, d) all data security is at memory level, e) all data indexed, sorted and searched based on the selected search algorithms are in memory, f) all logging functionality to refresh in-between transactions reside in memory. Therefore, the processing speed of database query will take advantage of speed of RAM (Random Access Memory) without sacrifice any speed losing on Hard disk I/O. Not only the whole database is running in RAM, but also all or pre-selected database table columns are default to be indexed. All internal processing of database query is based on indexed columns.

Abstract: A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other computer(s) equipped with a memory server on a distributed network. A memory backup and recovery as an optional subsystem of the Distributed Memory Computing system is also disclosed. A Network Attached Memory (herein called “NAM” or “NAM Box” or “NAM Server”) appliance is disclosed as a dedicated memory-sharing device attached to a network. A Memory Area Network (herein called “MAN”) is further disclosed, such a network is a network of memory device(s) or memory server(s) which provide memory sharing service to memory-demanding computer(s) or the like, when one memory device or memory server fails, its service will seamlessly transfer to other memory device(s) or memory server(s).

Abstract: A computing environment for a device having a processor, a device memory and an operating system. A first process running in the operating system has a memory and a memory cache. A second process running in the operating system has a second process memory accessible to the first process. A communication channel between the first process and second process makes the second process memory available for the first process memory to use. The device memory is sectioned into memory blocks, each having a starting address. A block ID identifies the memory block. Data is stored in various memory units of the memory block. An offset ID identifies the memory unit. A DMCE Virtual address contains the offset ID, the block Id and a device ID for identifying the memory unit. The DMCE virtual address of a memory unit used for the memory function is copied into the memory cache.

Abstract: A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other computer(s) equipped with a memory server on a distributed network. A memory backup and recovery as an optional subsystem of the Distributed Memory Computing system is also disclosed. A Network Attached Memory (herein called “NAM” or “NAM Box” or “NAM Server”) appliance is disclosed as a dedicated memory-sharing device attached to a network. A Memory Area Network (herein called “MAN”) is further disclosed, such a network is a network of memory device(s) or memory server(s) which provide memory sharing service to memory-demanding computer(s) or the like, when one memory device or memory server fails, its service will seamlessly transfer to other memory device(s) or memory server(s).

Abstract: A method and system for creating and searching a central linked list comprising a parent node which is situated at the center of a plurality of child nodes. Each child node has two double linked list pointers. One pointer points to the next child node, and the other pointer points to the parent node. Thus, matched data obtained at several child nodes moves immediately back to the parent simultaneously. The parent node contains the memory address and name of central linked list, a description of central linked list, and a description of the relationship between other parent nodes, as well as the relationship between each child node to its specific parent node. Each child node contains a node address, an attribute comprised of some or all of the stored data field and a link to the full data content that may reside on a file or in a database. Memory storage of the structure information is stored in system memory, such as, RAM.

Abstract: A computing environment for a device having a processor, a device memory and an operating system. A first process running in the operating system has a memory and a memory cache. A second process running in the operating system has a second process memory accessible to the first process. A communication channel between the first process and second process makes the second process memory available for the first process memory to use. The device memory is sectioned into memory blocks, each having a starting address. A block ID identifies the memory block. Data is stored in various memory units of the memory block. An offset ID identifies the memory unit. A DMCE Virtual address contains the offset ID, the block Id and a device ID for identifying the memory unit. The DMCE virtual address of a memory unit used for the memory function is copied into the memory cache.

Abstract: A method and system for creating and searching a central linked list comprising a parent node which is situated at the center of a plurality of child nodes. Each child node has two double linked list pointers. One pointer points to the next child node, and the other pointer points to the parent node. Thus, matched data obtained at several child nodes moves immediately back to the parent simultaneously. The parent node contains the memory address and name of central linked list, a description of central linked list, and a description of the relationship between other parent nodes, as well as the relationship between each child node to its specific parent node. Each child node contains a node address, an attribute comprised of some or all of the stored data field and a link to the full data content that may reside on a file or in a database. Memory storage of the structure information is stored in system memory, such as, RAM.