Patents by Inventor Jonathan Vu
Jonathan Vu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260072944Abstract: In accordance with an embodiment, described herein is a system and method for automated data warehouse creation and extension from user natural language requests. A data augmentation system, operating on one or more computers, can receive a natural language input from a user, including an instruction to augment a set of data, for example to create a fact/dimension, or to extend an existing data entity by bringing additional columns from a source data and publishing the combined data to a target data warehouse instance. The system determines an understanding associated with the user instruction in plain-language terms (for example, “extend sales order transactions with approval status”), and determines and performs a corresponding course of actions to create, extend, or otherwise augment the set of data, without requirement for the user to have a detailed knowledge of the data warehouse, its schemas, or other data dependencies.Type: ApplicationFiled: May 15, 2025Publication date: March 12, 2026Inventors: Sukanya Manna, Saugata Chowdhury, Somashekhar Pammar, Jonathan Vu, Sandeep Kadagathur Srinivasa Rao, Kamal Awasthi, Ritendra Bhattacharya, Saurav Mohapatro, Krishnan Ramanathan, Karthik Bangalore Mani, Akash Baviskar, Dipawesh Pawar, Mayank Bansal, Jagdish Chand, Vikas Agrawal
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Publication number: 20230029517Abstract: In some examples, a computing device can include a component device, a battery, and a memory resource storing instructions to cause a processing resource to determine an operating mode of the computing device, in response to the operating mode being a charging mode, cause the battery to charge, in response to the operating mode being a system battery mode, cause the battery to power the computing device, and in response to the operating mode being a battery reserve mode, cause the battery to power the component device in absence of powering other components of the computing device.Type: ApplicationFiled: January 22, 2020Publication date: February 2, 2023Applicant: Hewlett-Packard Development Company, L.P.Inventors: Isaac Lagnado, Christopher Charles Mohrman, Charles J. Stancil, Steven Petit, Jonathan Vu, Monji G. Jabori
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Publication number: 20230004514Abstract: In some examples, a system comprises: a socket; a controller coupled to the socket; a storage device comprising machine-readable instructions; and a processor coupled to the controller and the storage device, wherein execution of the machine-readable instructions causes the processor to: detect a Secure Digital (SD) card in the socket via the controller; prompt a user to select a communication protocol to be utilized by the system to communicate with the SD card; and enable the system to communicate with the SD card based on the user selection.Type: ApplicationFiled: December 12, 2019Publication date: January 5, 2023Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Monji G. Jabori, Rahul Lakdawala, Jonathan Vu
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Patent number: 11232061Abstract: In some examples, an adapter includes a COMPACTFLASH EXPRESS (CFX) connector interface to connect to a CFX connector of a computer, and a device connector interface to connect to any of a plurality of different devices comprising different types of interfaces. The device connector interface includes an indicator settable to any of a plurality of different states to represent a respective type of the different types of interfaces when a device is connected to the adapter, and the CFX connector interface comprising an indicator connected to the indicator of the device connector interface.Type: GrantFiled: June 11, 2018Date of Patent: January 25, 2022Assignee: Hewlett-Packard Development Company, L.P.Inventors: Monji G. Jabori, Byron A. Alcorn, Jonathan Vu
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Publication number: 20210157763Abstract: In some examples, an adapter includes a COMPACTFLASH EXPRESS (CFX) connector interface to connect to a CFX connector of a computer, and a device connector interface to connect to any of a plurality of different devices comprising different types of interfaces. The device connector interface includes an indicator settable to any of a plurality of different states to represent a respective type of the different types of interfaces when a device is connected to the adapter, and the CFX connector interface comprising an indicator connected to the indicator of the device connector interface.Type: ApplicationFiled: June 11, 2018Publication date: May 27, 2021Applicant: Hewlett-Packard Development Company, L.P.Inventors: Monji G. Jabori, Byron A. Alcorn, Jonathan Vu
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Publication number: 20210089404Abstract: Example implementations relate to memory power termination delays. In some examples, a computing system may include a memory storage device, a memory controller, an input/output (I/O) controller, a power management controller (PMC), a bus compliant with an Enhanced Serial Peripheral Interface (eSPI) protocol, and a power control gating. The input/output controller may transmit a power termination command to the power management controller via the bus compliant with the eSPI protocol. Upon a receipt of the power termination command, the PMC may initiate a delay period of an assertion of the power termination command to the power control gating and transmit a memory transfer command to the memory controller included in the memory storage device. The memory controller, upon receipt of the memory transfer command, may move data stored in volatile memory to non-volatile memory included in the memory storage device.Type: ApplicationFiled: June 11, 2018Publication date: March 25, 2021Applicant: Hewlett-Packard Development Company, L.P.Inventors: Monji G. Jabori, Byron A. Alcorn, Jonathan Vu
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Publication number: 20200210367Abstract: A system may include a computing device. The computing device may include an optical disc drive (ODD) bay, wherein an ODD is not present in the ODD bay. The system may further include an ODD connector. The system may also include an external serial AT attachment (eSATA) device located in an opening of the ODD bay for housing the non-present ODD and coupled to the computing device by the ODD connector at the ODD bay.Type: ApplicationFiled: September 6, 2017Publication date: July 2, 2020Inventors: Monji G. Jabori, Jonathan Vu
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Patent number: 7318076Abstract: A comprehensive Memory-Resident Database Management System architecture and implementation is disclosed where a) all data storage in database is in memory, b) all database management functionality is in memory except backup and recovery storage based on hard disk, c) all database objects including tables, views, triggers, procedures, functions . . . are in memory, d) all data security is at memory level, e) all data indexed, sorted and searched based on the selected search algorithms are in memory, f) all logging functionality to refresh in-between transactions reside in memory. Therefore, the processing speed of database query will take advantage of speed of RAM (Random Access Memory) without sacrifice any speed losing on Hard disk I/O. Not only the whole database is running in RAM, but also all or pre-selected database table columns are default to be indexed. All internal processing of database query is based on indexed columns.Type: GrantFiled: January 22, 2003Date of Patent: January 8, 2008Assignee: Intelitrac, Inc.Inventors: Tianlong Chen, Jonathan Vu
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Patent number: 7149855Abstract: A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other computer(s) equipped with a memory server on a distributed network. A memory backup and recovery as an optional subsystem of the Distributed Memory Computing system is also disclosed. A Network Attached Memory (herein called “NAM” or “NAM Box” or “NAM Server”) appliance is disclosed as a dedicated memory-sharing device attached to a network. A Memory Area Network (herein called “MAN”) is further disclosed, such a network is a network of memory device(s) or memory server(s) which provide memory sharing service to memory-demanding computer(s) or the like, when one memory device or memory server fails, its service will seamlessly transfer to other memory device(s) or memory server(s).Type: GrantFiled: January 23, 2004Date of Patent: December 12, 2006Assignee: Intelitrac, Inc.Inventors: Tianlong Chen, Jonathan Vu, Yingbin Wang
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Patent number: 7051158Abstract: A computing environment for a device having a processor, a device memory and an operating system. A first process running in the operating system has a memory and a memory cache. A second process running in the operating system has a second process memory accessible to the first process. A communication channel between the first process and second process makes the second process memory available for the first process memory to use. The device memory is sectioned into memory blocks, each having a starting address. A block ID identifies the memory block. Data is stored in various memory units of the memory block. An offset ID identifies the memory unit. A DMCE Virtual address contains the offset ID, the block Id and a device ID for identifying the memory unit. The DMCE virtual address of a memory unit used for the memory function is copied into the memory cache.Type: GrantFiled: April 30, 2003Date of Patent: May 23, 2006Assignee: InteliTrac, Inc.Inventors: Tianlong Chen, Yingbin Wang, Yinong Wei, Jonathan Vu
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Patent number: 7043623Abstract: A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other computer(s) equipped with a memory server on a distributed network. A memory backup and recovery as an optional subsystem of the Distributed Memory Computing system is also disclosed. A Network Attached Memory (herein called “NAM” or “NAM Box” or “NAM Server”) appliance is disclosed as a dedicated memory-sharing device attached to a network. A Memory Area Network (herein called “MAN”) is further disclosed, such a network is a network of memory device(s) or memory server(s) which provide memory sharing service to memory-demanding computer(s) or the like, when one memory device or memory server fails, its service will seamlessly transfer to other memory device(s) or memory server(s).Type: GrantFiled: January 22, 2003Date of Patent: May 9, 2006Assignee: InteliTrac, Inc.Inventors: Tianlong Chen, Jonathan Vu, Yingbin Wang
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Publication number: 20050015396Abstract: A method and system for creating and searching a central linked list comprising a parent node which is situated at the center of a plurality of child nodes. Each child node has two double linked list pointers. One pointer points to the next child node, and the other pointer points to the parent node. Thus, matched data obtained at several child nodes moves immediately back to the parent simultaneously. The parent node contains the memory address and name of central linked list, a description of central linked list, and a description of the relationship between other parent nodes, as well as the relationship between each child node to its specific parent node. Each child node contains a node address, an attribute comprised of some or all of the stored data field and a link to the full data content that may reside on a file or in a database. Memory storage of the structure information is stored in system memory, such as, RAM.Type: ApplicationFiled: July 16, 2004Publication date: January 20, 2005Inventor: Jonathan Vu
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Publication number: 20040221122Abstract: A computing environment for a device having a processor, a device memory and an operating system. A first process running in the operating system has a memory and a memory cache. A second process running in the operating system has a second process memory accessible to the first process. A communication channel between the first process and second process makes the second process memory available for the first process memory to use. The device memory is sectioned into memory blocks, each having a starting address. A block ID identifies the memory block. Data is stored in various memory units of the memory block. An offset ID identifies the memory unit. A DMCE Virtual address contains the offset ID, the block Id and a device ID for identifying the memory unit. The DMCE virtual address of a memory unit used for the memory function is copied into the memory cache.Type: ApplicationFiled: April 30, 2003Publication date: November 4, 2004Inventors: Tianlong Chen, Yingbin Wang, Yinong Wei, Jonathan Vu
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Patent number: 6785674Abstract: A method and system for creating and searching a central linked list comprising a parent node which is situated at the center of a plurality of child nodes. Each child node has two double linked list pointers. One pointer points to the next child node, and the other pointer points to the parent node. Thus, matched data obtained at several child nodes moves immediately back to the parent simultaneously. The parent node contains the memory address and name of central linked list, a description of central linked list, and a description of the relationship between other parent nodes, as well as the relationship between each child node to its specific parent node. Each child node contains a node address, an attribute comprised of some or all of the stored data field and a link to the full data content that may reside on a file or in a database. Memory storage of the structure information is stored in system memory, such as, RAM.Type: GrantFiled: January 17, 2003Date of Patent: August 31, 2004Assignee: InteliTrac, Inc.Inventor: Jonathan Vu
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Publication number: 20040151018Abstract: A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other computer(s) equipped with a memory server on a distributed network. A memory backup and recovery as an optional subsystem of the Distributed Memory Computing system is also disclosed. A Network Attached Memory (herein called “NAM” or “NAM Box” or “NAM Server”) appliance is disclosed as a dedicated memory-sharing device attached to a network. A Memory Area Network (herein called “MAN”) is further disclosed, such a network is a network of memory device(s) or memory server(s) which provide memory sharing service to memory-demanding computer(s) or the like, when one memory device or memory server fails, its service will seamlessly transfer to other memory device(s) or memory server(s).Type: ApplicationFiled: January 23, 2004Publication date: August 5, 2004Inventors: Tianlong Chen, Jonathan Vu, Yingbin Wang
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Publication number: 20040143718Abstract: A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other computer(s) equipped with a memory server on a distributed network. A memory backup and recovery as an optional subsystem of the Distributed Memory Computing system is also disclosed. A Network Attached Memory (herein called “NAM” or “NAM Box” or “NAM Server”) appliance is disclosed as a dedicated memory-sharing device attached to a network. A Memory Area Network (herein called “MAN”) is further disclosed, such a network is a network of memory device(s) or memory server(s) which provide memory sharing service to memory-demanding computer(s) or the like, when one memory device or memory server fails, its service will seamlessly transfer to other memory device(s) or memory server(s).Type: ApplicationFiled: January 22, 2003Publication date: July 22, 2004Inventors: Tianlong Chen, Jonathan Vu, Yingbin Wang
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Publication number: 20040143582Abstract: A method and system for creating and searching a central linked list comprising a parent node which is situated at the center of a plurality of child nodes. Each child node has two double linked list pointers. One pointer points to the next child node, and the other pointer points to the parent node. Thus, matched data obtained at several child nodes moves immediately back to the parent simultaneously. The parent node contains the memory address and name of central linked list, a description of central linked list, and a description of the relationship between other parent nodes, as well as the relationship between each child node to its specific parent node. Each child node contains a node address, an attribute comprised of some or all of the stored data field and a link to the full data content that may reside on a file or in a database. Memory storage of the structure information is stored in system memory, such as, RAM.Type: ApplicationFiled: January 17, 2003Publication date: July 22, 2004Inventor: Jonathan Vu
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Publication number: 20040143562Abstract: A comprehensive Memory-Resident Database Management System architecture and implementation is disclosed where a) all data storage in database is in memory, b) all database management functionality is in memory except backup and recovery storage based on hard disk, c) all database objects including tables, views, triggers, procedures, functions . . . are in memory, d) all data security is at memory level, e) all data indexed, sorted and searched based on the selected search algorithms are in memory, f) all logging functionality to refresh in-between transactions reside in memory. Therefore, the processing speed of database query will take advantage of speed of RAM (Random Access Memory) without sacrifice any speed losing on Hard disk I/O. Not only the whole database is running in RAM, but also all or pre-selected database table columns are default to be indexed. All internal processing of database query is based on indexed columns.Type: ApplicationFiled: January 22, 2003Publication date: July 22, 2004Inventors: Tianlong Chen, Jonathan Vu