Abstract: A footprint based optimal characterization of intellectual property (IP) for more deterministic physical integration. The physical integration characteristics are based upon IP physical integration at an anchor point in a pre-defined IC platform. IP footprint characteristics are identified as fixed, variable or prioritized to each other, and bounding constraints are defined based on a set of characteristics for the IP, the platform characteristics and IC design requirements. The IP is physically synthesized using the bounding constraints. The synthesized IP is tested and the bounding constraints are iteratively modified until the characteristics of the synthesized IP are optimized/captured.

Abstract: The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration (“test backplane”) for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the “test backplane”. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the “test backplane”. These pre-exiting test structures may then be connected.

Abstract: A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set.

Abstract: A method and apparatus for a cache line cut through reduces the latency and memory bandwidth of a data processing system. By cutting through or forwarding a cache line to the next processing element, data that has been read from a local memory into a local cache and altered by a processing element need not be restored to the local memory before it is sent to its destination target processing element. By eliminating the write back to the local memory for direct write through to the destination, performance is increased because the bandwidth and latency are decreased. In a preferred embodiment, the processing elements may be contained within a network processor and the altered data may be a header in one network protocol which needs to be modified to another protocol before transfer of the data along the network. Transfer of the data may be to another network processor, another processing element, or to another memory.

Abstract: A method and apparatus are disclosed for providing an inline data service within a data processing system coupled to a communications network. The data processing system includes a host memory. According to the present invention, the apparatus comprises an adapter memory for temporarily storing data communicated between the data processing system and the communications network and a memory access controller, which controls transfers of data between the adapter memory and the host memory. The apparatus further includes means for selectively performing a data transformation on data transferred between the adapter memory and the host memory, wherein the data transformation is performed during a transfer of the data such that data communication latency is reduced. In a second preferred embodiment of the present invention, a multibus data processing system has a processor and a first memory coupled to a first bus and a second memory coupled to a second bus.

Abstract: A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the virtual address frame offset and generates an offset and index. A frame map table indexes the virtual address map index and the selector generated index and generates a base address. The frame map table generated base address and the selector generated offset are combined to provide a physical address.

Abstract: Method and apparatus are provided for transmitting a stream of multimedia digital data over a distribution communications network. A multimedia stream server segments the multimedia digital data stream into data blocks on a first boundary and a second boundary. The first boundary is a set number of transport system data packets and the second boundary is a transport system data packet including a timestamp. A scheduler schedules the segmented data blocks for transmission. The multimedia stream server decodes the segmented data blocks to locate the timestamps and matches the transmission of the located timestamp data block with a time value indicated by the timestamp. The set number of transport system data packets can be determined at connection setup and is not a predetermined value for all sessions. At the receiver, batch processing of received multimedia data can be provided.

Abstract: A method and apparatus for scheduling the transmission of a number of data streams over a common communications link, where each of the data streams conforms to a corresponding set of flow control parameters. Each of the data streams to be transmitted on the communications link is stored in a corresponding queue. The status of each queue is maintained, and a target transmission time is calculated for each queue. Signals are then generated for each queue at a time at least after the target transmission time, and these signals are used to indicate to a corresponding queue that is can transmit a cell on the link. Upon reception of a corresponding signal, a queue then transmits at least one cell onto the communications link.

Abstract: Method and apparatus are provided for transmitting a stream of multimedia digital data over a distribution communications network. A multimedia stream server segments the multimedia digital data stream into data blocks on a first boundary and a second boundary. The first boundary is a set number of transport system data packets and the second boundary is a transport system data packet including a timestamp. A scheduler schedules the segmented data blocks for transmission. The multimedia stream server decodes the segmented data blocks to locate the timestamps and matches the transmission of the located timestamp data block with a time value indicated by the timestamp. The set number of transport system data packets can be determined at connection setup and is not a predetermined value for all sessions. At the receiver, batch processing of received multimedia data can be provided.

Abstract: A first-in, first-out queue is implemented on two memory elements by enqueuing and dequeuing items from a first memory element and by swapping middle portions of the queue between the first memory element and the second memory whenever the first memory element is sufficiently filled. Where the second element is system memory for a computer system, queue length can be allowed to grow almost arbitrarily while preserving the performance of first memory element.

Abstract: A method and a system in a distributed data processing network for enhancing the processing of a plurality of related data packets received at a receiving station within the distributed data processing network, each of the data packets having a header associated herewith includes sequentially receiving a number of data packets at the receiving station. Next, the header associated with a first data packet is examined and predicted profile is generated for comparison with a related subsequent data packet. The next data packet received is then compared with the predicted profile to determine whether or not the two data packets may be consolidated.