Abstract: A list of program instructions are mapped into memory addresses to form an executable program by simulating their execution in turn so as to determine a memory address of a next program instruction to be executed. That memory address is then examined to determine if a program instruction has already been mapped thereto. If the memory address is empty, then the next program instruction from the list is mapped to that empty memory address and the execution of that next program instruction is simulated and the process repeated. If the memory address is not empty, then the program instruction read from that memory address is simulated again and the process repeated.

Abstract: A test program for a data processing apparatus is produced using a genetic algorithm which mutates instances being ordered lists of program instructions within a population forming the test program. The populations are evaluated using a metric by which the population as a whole is scored for its stimulation of predetermined functional points within the data processing apparatus when a determination is being made as to whether or not a particular instance should be swapped in or out of the population.

Abstract: Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to deliberately introduced test faults, with expected execution outcomes previously derived for that candidate program to determine the sensitivity of that candidate program to the faults which are introduced. This score can be fed back into the genetic algorithm mutation to converge the mutation process upon appropriately fault sensitive software built in self test program code.

Abstract: The present invention relates to a data processing apparatus and method for compiling application code. The data processing apparatus comprises a processor, and a compiler for compiling application code to generate instructions for execution by the processor. Furthermore, a non-invasive trace unit is coupled to the processor for generating, from input signals received from the processor, trace signals indicative of the instructions being executed by the processor. The compiler is then arranged to control the compilation of the application code dependent on the trace signals. The non-invasive nature of the trace unit enables it to generate trace signals that can be used to produce profiling information for use by the compiler without altering the behaviour of the code being executed by the processor, and accordingly provides a significantly improved technique for obtaining profiling information for use in feedback driven optimization compilation techniques.

Abstract: An integrated circuit containing a plurality of data processing circuit elements 4, 6, 8, 10, 12, 14 and 16 is provided with a configuration data memory 12. Upon initialisation of the integrated circuit 2, configuration data is read from the configuration data memory 12 and used to set up configuration program software 26 that controls the interaction between application program software 18, 20, 22 and the integrated circuit 2. The configuration data is automatically formed from a human readable hierarchical description of the integrated circuit 2 in the form of an ASN.1 description.

Abstract: The present invention relates to a data processing apparatus and method for compiling application code. The data processing apparatus comprises a processor, and a compiler for compiling application code to generate instructions for execution by the processor. Furthermore, a non-invasive trace unit is coupled to the processor for generating, from input signals received from the processor, trace signals indicative of the instructions being executed by the processor. The compiler is then arranged to control the compilation of the application code dependent on the trace signals. The non-invasive nature of the trace unit enables it to generate trace signals that can be used to produce profiling information for use by the compiler without altering the behaviour of the code being executed by the processor, and accordingly provides a significantly improved technique for obtaining profiling information for use in feedback driven optimisation compilation techniques.

Abstract: An integrated circuit containing a plurality of data processing circuit elements 4, 6, 8, 10, 12, 14 and 16 is provided with a configuration data memory 12. Upon initialisation of the integrated circuit 2, configuration data is read from the configuration data memory 12 and used to set up configuration program software 26 that controls the interaction between application program software 18, 20, 22 and the integrated circuit 2. The configuration data is automatically formed from a human readable hierarchical description of the integrated circuit 2 in the form of an ASN.1 description.

Abstract: An integrated circuit containing a plurality of data processing circuit elements 4, 6, 8, 10, 12, 14 and 16 is provided with a configuration data memory 12. Upon initialisation of the integrated circuit 2, configuration data is read from the configuration data memory 12 and used to set up configuration program software 26 that controls the interaction between application program software 18, 20, 22 and the integrated circuit 2. The configuration data is automatically formed from a human readable hierarchical description of the integrated circuit 2 in the form of an ASN.1 description.