Abstract: A system including a bus, a processor coupled to the bus, a non-volatile memory coupled to the bus, circuitry for providing a detected condition, and a secure controller. The secure controller is coupled to the circuitry for providing a detected condition and to selectively enable communication of information between the non-volatile memory and the bus in response to the detected condition.

Abstract: A system including a bus, a processor coupled to the bus, a non-volatile memory coupled to the bus, circuitry for providing a detected condition, and a secure controller. The secure controller is coupled to the circuitry for providing a detected condition and to selectively enable communication of information between the non-volatile memory and the bus in response to the detected condition.

Abstract: An apparatus includes a memory device and a microcontroller device integrated with the memory device. The microcontroller device is adapted to be communicatively coupled to a processor device and is configured to manage access by the processor device to data stored on the memory device. Managing access by the processor device to the data stored on the memory device includes setting an access permission for controlled data stored by the memory device based on authorization data stored in the memory device. Managing access by the processor device further includes receiving, from the processor device, a request to access the controlled data. Managing access by the processor device further includes determining whether to initiate access to the controlled data by the processor device based on the access permission.

Abstract: An apparatus includes a memory device and a microcontroller device integrated with the memory device. The microcontroller device is adapted to be communicatively coupled to a processor device and is configured to manage access by the processor device to data stored on the memory device. Managing access by the processor device to the data stored on the memory device includes setting an access permission for controlled data stored by the memory device based on authorization data stored in the memory device. Managing access by the processor device further includes receiving, from the processor device, a request to access the controlled data. Managing access by the processor device further includes determining whether to initiate access to the controlled data by the processor device based on the access permission.

Abstract: A system including a bus, a processor coupled to the bus, a non-volatile memory coupled to the bus, circuitry for providing a detected condition, and a secure controller. The secure controller is coupled to the circuitry for providing a detected condition and to selectively enable communication of information between the non-volatile memory and the bus in response to the detected condition.

Abstract: An apparatus includes a memory device and a microcontroller device integrated with the memory device. The microcontroller device is adapted to be communicatively coupled to a processor device and is configured to manage access by the processor device to data stored on the memory device. Managing access by the processor device to the data stored on the memory device includes setting an access permission for controlled data stored by the memory device based on authorization data stored in the memory device. Managing access by the processor device further includes receiving, from the processor device, a request to access the controlled data. Managing access by the processor device further includes determining whether to initiate access to the controlled data by the processor device based on the access permission.

Abstract: An integrated circuit and method of performing a reliability screen of an electrically programmable non-volatile memory array in the integrated circuit. At a first memory address of the array, a most stringent value of a sensing reference level at which correct data are read is identified. The remainder of the addresses of the array are evaluated in sequence, beginning at the value determined for the first address, and incrementally adjusting the sensing reference level for each, if necessary, until correct data are read at that address. The sensing reference level may be a reference current applied to a sense amplifier, against which read current from the addressed memory cell is compared, or may be control gate voltage applied to the control gate of a floating-gate transistor in the addressed memory cell.

Abstract: An integrated circuit and method of performing a reliability screen of an electrically programmable non-volatile memory array in the integrated circuit. At a first memory address of the array, a most stringent value of a sensing reference level at which correct data are read is identified. The remainder of the addresses of the array are evaluated in sequence, beginning at the value determined for the first address, and incrementally adjusting the sensing reference level for each, if necessary, until correct data are read at that address. The sensing reference level may be a reference current applied to a sense amplifier, against which read current from the addressed memory cell is compared, or may be control gate voltage applied to the control gate of a floating-gate transistor in the addressed memory cell.

Abstract: An integrated circuit and method of performing a reliability screen of an electrically programmable non-volatile memory array in the integrated circuit. At a first memory address of the array, a most stringent value of a sensing reference level at which correct data are read is identified. The remainder of the addresses of the array are evaluated in sequence, beginning at the value determined for the first address, and incrementally adjusting the sensing reference level for each, if necessary, until correct data are read at that address. The sensing reference level may be a reference current applied to a sense amplifier, against which read current from the addressed memory cell is compared, or may be control gate voltage applied to the control gate of a floating-gate transistor in the addressed memory cell.