Patents by Inventor Jonathan Y. Zhang

Jonathan Y. Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pipelining access to serialization tokens on a bus
    Patent number: 7139854
    Abstract: Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: November 21, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Y. Zhang, Robert J. P. Nychka, Eric L. P. Badi
  • Reducing tag-ram accesses and accelerating cache operation during cache miss
    Patent number: 6983346
    Abstract: This invention is a cache memory employing a tag bypass controller to detect a memory access to the same cache line as a last cache miss address and a last cache hit address. This information is uses for efficient data accesses and forwarding. Registers store the last miss-address and the last hit-address and corresponding valid flags. These hardware features allow reduced tag-RAM accesses and greatly reduce the latency required to fully re-stock a missed cache line.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: January 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Jonathan Y. Zhang
  • Pipelining access to serialization tokens on a bus
    Publication number: 20040255066
    Abstract: Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 16, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Jonathan Y. Zhang, Robert J.P. Nychka, Eric Badi
  • Reducing tag-ram accesses and accelerating cache operation during cache miss
    Publication number: 20040024967
    Abstract: This invention is a cache memory employing a tag bypass controller to detect a memory access to the same cache line as a last cache miss address and a last cache hit address. This information is uses for efficient data accesses and forwarding. Registers store the last miss-address and the last hit-address and corresponding valid flags. These hardware features allow reduced tag-RAM accesses and greatly reduce the latency required to fully re-stock a missed cache line.
    Type: Application
    Filed: May 9, 2003
    Publication date: February 5, 2004
    Inventor: Jonathan Y. Zhang