Patents by Inventor Jonathon E. Colburn
Jonathon E. Colburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10545189Abstract: In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.Type: GrantFiled: October 27, 2016Date of Patent: January 28, 2020Assignee: NVIDIA CORPORATIONInventors: Milind Sonawane, Amit Sanghani, Jonathon E. Colburn, Bala Tarun Nelapatla, Shantanu Sarangi, Rajendra Kumar reddy.S, Sailendra Chadalavada
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Patent number: 10451676Abstract: A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.Type: GrantFiled: October 27, 2016Date of Patent: October 22, 2019Assignee: Nvidia CorporationInventors: Milind Sonawane, Amit Sanghani, Shantanu Sarangi, Jonathon E. Colburn, Bala Tarun Nelapatla, Sailendra Chadalavda, Rajendra Kumar Reddy.S, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha
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Patent number: 10444280Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.Type: GrantFiled: October 27, 2016Date of Patent: October 15, 2019Assignee: NVIDIA CORPORATIONInventors: Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Sailendra Chadalavda, Jonathon E. Colburn, Kevin Wilder, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha
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Patent number: 10317463Abstract: A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.Type: GrantFiled: October 27, 2016Date of Patent: June 11, 2019Assignee: NVIDIA CORPORATIONInventors: Milind Sonawane, Amit Sanghani, Jonathon E. Colburn, Rajendra Kumar reddy.S, Bala Tarun Nelapatla, Sailendra Chadalavda, Shantanu Sarangi
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Patent number: 10281524Abstract: In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.Type: GrantFiled: October 27, 2016Date of Patent: May 7, 2019Assignee: NVIDIA CORPORATIONInventors: Sailendra Chadalavda, Shantanu Sarangi, Milind Sonawane, Amit Sanghani, Jonathon E. Colburn, Dan Smith, Jue Wu, Mahmut Yilmaz
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Patent number: 9829536Abstract: In one embodiment, a multiple input signature register (MISR) shadow works with a MISR to compress test responses of a layout partition in a functional region of an integrated circuit. In operation, for each test pattern in a test pattern split, the MISR generates a MISR signature based on the responses of the layout partition. As the test patterns in the test pattern split execute, the MISR shadow accumulates the MISR signatures and stores the result as MISR shadow data. After the final test pattern included in the test pattern split executes, the MISR shadow combines the bits in the MISR shadow data to form a single bit MISR shadow status that indicates whether the layout partition, and therefore the functional region, responds properly to the test pattern split. By efficiently summarizing the test responses, the MISR shadow optimizes the resources required to identify defective functional regions.Type: GrantFiled: February 3, 2016Date of Patent: November 28, 2017Assignee: NVIDIA CORPORATIONInventors: Milind Sonawane, Jonathon E. Colburn, Amit Sanghani
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Publication number: 20170219652Abstract: In one embodiment, a multiple input signature register (MISR) shadow works with a MISR to compress test responses of a layout partition in a functional region of an integrated circuit. In operation, for each test pattern in a test pattern split, the MISR generates a MISR signature based on the responses of the layout partition. As the test patterns in the test pattern split execute, the MISR shadow accumulates the MISR signatures and stores the result as MISR shadow data. After the final test pattern included in the test pattern split executes, the MISR shadow combines the bits in the MISR shadow data to form a single bit MISR shadow status that indicates whether the layout partition, and therefore the functional region, responds properly to the test pattern split. By efficiently summarizing the test responses, the MISR shadow optimizes the resources required to identify defective functional regions.Type: ApplicationFiled: February 3, 2016Publication date: August 3, 2017Inventors: Milind SONAWANE, Jonathon E. COLBURN, Amit SANGHANI
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Publication number: 20170115352Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.Type: ApplicationFiled: October 27, 2016Publication date: April 27, 2017Inventors: Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Sailendra Chadalavda, Jonathon E. Colburn, Kevin Wilder, Mahmut Yilmaz
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Publication number: 20170115345Abstract: A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.Type: ApplicationFiled: October 27, 2016Publication date: April 27, 2017Inventors: Milind Sonawane, Amit Sanghani, Shantanu Sarangi, Jonathon E. Colburn, Bala Tarun Nelapatla, Sailendra Chadalavda, Rajendra Kumar reddy.S, Mahmut Yilmaz
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Publication number: 20170115338Abstract: In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.Type: ApplicationFiled: October 27, 2016Publication date: April 27, 2017Inventors: Sailendra Chadalavda, Shantanu Sarangi, Milind Sonawane, Amit Sanghani, Jonathon E. Colburn, Dan Smith, Jue Wu, Mahmut Yilmaz
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Publication number: 20170115353Abstract: In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.Type: ApplicationFiled: October 27, 2016Publication date: April 27, 2017Inventors: Milind Sonawane, Amit Sanghani, Jonathon E. Colburn, Bala Tarun Nelapatla, Shantanu Sarangi, Rajendra Kumar reddy.S
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Publication number: 20170115346Abstract: A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.Type: ApplicationFiled: October 27, 2016Publication date: April 27, 2017Inventors: Milind Sonawane, Amit Sanghani, Jonathon E. Colburn, Rajendra Kumar reddy.S, Bala Tarun Nelapatla, Sailendra Chadalavda, Shantanu Sarangi