Abstract: Network communication apparatus for connection to a computer that includes a host processor, a host memory and at least first and second root ports. The apparatus includes a network port, for connection to a packet communication network, and first and second host bus interfaces, for connection via respective first and second peripheral component buses to the first and second root ports, respectively. Packet processing logic is coupled between the network port and the first and second host bus interfaces and includes first and second direct memory access (DMA) engines to read data from the host memory via the first and second root ports, respectively, for transmission via the network port, while exposing the network port to the host computer only through the first host bus interface.

Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may record permissions granting entities access to physical addresses in physical address access permissions tables (PAAPTs) responsive to the address translation. The security of address translation services may be increased based at least on verifying memory access requests are authorized using the PAAPTs. For example, an entity identifier included in a request may be used to locate a corresponding PAAPT, and a physical address may be extracted from the request and used to locate an entry indicating whether an entity corresponding to the entity identifier has permission to access the physical address. Where the entity has permission, the system may perform the memory access using the physical address. Otherwise an error or fault code may be provided in response to the request.

Abstract: In one embodiment, a system includes a peripheral device, which includes an interface to receive from a virtual machine (VM) running on a host device, over a communication data bus, a request for timing data derived from a time measurement dialogue, the host device maintaining a master clock time, a hardware clock to maintain a peripheral device clock time, and processing circuitry to transform the master clock time to a frame of reference of the VM, and provide to the VM, over the communication data bus, the timing data based on the peripheral device clock time, and the master clock time transformed to the frame of reference of the VM.

Abstract: systems, computer program products, and methods are described for an endpoint device configured for secure data transmission within a network. An example endpoint device may include a network interface configured to receive a communication request from a peer endpoint device, and an access control unit configured to determine whether a peer endpoint device is IDE qualified based on the communication request. If the peer endpoint device is IDE qualified, the access control unit authorizes the communication request, allowing secure communication between the devices. If the peer endpoint device is not IDE qualified, the access control unit transmits the communication request to a root port for further authorization, verifying that only IDE-qualified devices are permitted to communicate directly.

Abstract: Systems, computer program products, and methods are described for secure data transmission. An example system includes a first end-point device, an intermediate device, and a second-end point device. The first end-point device determines the format requirements of the communication link between the first end-point device and the intermediate device, and the communication link intermediate device and the second end-point device. Based on the format requirements, the first end-point device configures the data packet for transmission, such that the data packet, when received at the intermediate device, is re-configured and routed to the second end-point device. When the second end-point device receives the data packet, it verifies the data packet to confirm that the packet has maintained its integrity throughout transit.

Abstract: Apparatuses, systems, and techniques to optimize processor resources at a user-defined level. In at least one embodiment, priority of one or more tasks are adjusted to prevent one or more other dependent tasks from entering an idle state due to lack of resources to consume.

Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may incorporate the physical address and a signature of the physical address generated using a private key into a translated address field of a response to a translation request. An endpoint may treat the combination as a translated address by storing it in an entry of a translation cache, and accessing the entry for inclusion in a memory access request. The host may generate a signature of the translated address from the request using the private key, with the result being compared to the signature from the request. The memory access request may be verified when the compared values match, and the memory access may be performed using the translated address.

Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may record permissions granting entities access to physical addresses in physical address access permissions tables (PAAPTs) responsive to the address translation. The security of address translation services may be increased based at least on verifying memory access requests are authorized using the PAAPTs. For example, an entity identifier included in a request may be used to locate a corresponding PAAPT, and a physical address may be extracted from the request and used to locate an entry indicating whether an entity corresponding to the entity identifier has permission to access the physical address. Where the entity has permission, the system may perform the memory access using the physical address. Otherwise an error or fault code may be provided in response to the request.

Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may incorporate the physical address and a signature of the physical address generated using a private key into a translated address field of a response to a translation request. An endpoint may treat the combination as a translated address by storing it in an entry of a translation cache, and accessing the entry for inclusion in a memory access request. The host may generate a signature of the translated address from the request using the private key, with the result being compared to the signature from the request. The memory access request may be verified when the compared values match, and the memory access may be performed using the translated address.

Abstract: Apparatuses, systems, and techniques to optimize processor resources at a user-defined level. In at least one embodiment, priority of one or more tasks are adjusted to prevent one or more other dependent tasks from entering an idle state due to lack of resources to consume.

Abstract: Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.

Abstract: Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.