Patents by Inventor Jones Wang
Jones Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9754849Abstract: An organic-inorganic hybrid structure is described for integrated circuit packages. In one example, an integrated circuit package includes a ceramic frame having a top side and a bottom side, the top side having a pocket with a bottom floor and a plurality of conductive through holes in the bottom floor, an integrated circuit die attached to the bottom floor over the conductive through holes, and a redistribution layer on the bottom side connected to the conductive through holes.Type: GrantFiled: December 23, 2014Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Plory Huang, Henry Su, Chee Key Chung, Ryan Ong, Jones Wang, Daniel Hsieh
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Publication number: 20160181169Abstract: An organic-inorganic hybrid structure is described for integrated circuit packages. In one example, an integrated circuit package includes a ceramic frame having a top side and a bottom side, the top side having a pocket with a bottom floor and a plurality of conductive through holes in the bottom floor, an integrated circuit die attached to the bottom floor over the conductive through holes, and a redistribution layer on the bottom side connected to the conductive through holes.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: PLORY HUANG, Henry Su, Chee Key Chung, Ryan Ong, Jones Wang, Daniel Hsieh
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Patent number: 8478074Abstract: Various embodiments are disclosed relating to providing multiple and native representations of an image. According to an example embodiment, multiple realizations of an image may be generated and provided, rather than only a single realization, for example. Also, in another embodiment, the generation and output of multiple realizations may use one or more native objects to natively perform the transforms or image processing to provide the images or realizations.Type: GrantFiled: July 7, 2006Date of Patent: July 2, 2013Assignee: Microsoft CorporationInventors: Rajat Goel, Margaret L. Goodwin, Radu C. Margarint, Robert A. Wlodarczyk, Thomas W. Olsen, Wei-Chung Jones Wang
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Patent number: 8117277Abstract: An operating system to componentize file sharing is described, in which a file transport send object is executable on the operating system to designate a shared file for sharing, and in which a notification send object is executable on the operating system to notify of the shared file. An operating system to componentize file sharing is described, in which a file transport receive object is executable on the operating system to receive a shared file, and in which a notification receive object that is executable on the operating system to notify of the shared file.Type: GrantFiled: April 27, 2005Date of Patent: February 14, 2012Assignee: Microsoft CorporationInventors: Mark A. Nikiel, Ignatius Setiadi, Chun-Kit J. Chan, Kevin N. Kim, Shabbir A. Shahpurwala, Wei-Chung Jones Wang
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Patent number: 7390697Abstract: A new method is provided for the interface between a stress relieve interface layer of polyimide and a thereover created layer of mold compound. The invention provides for creating a pattern in the stress relieve layer of polyimide before the layer of mold compound is formed over the stress relieve layer of polyimide.Type: GrantFiled: February 17, 2005Date of Patent: June 24, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ken Chen, Chender Huang, Pei-Haw Tsao, Jones Wang, Hank Huang
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Publication number: 20080008392Abstract: Various embodiments are disclosed relating to providing multiple and native representations of an image. According to an example embodiment, multiple realizations of an image may be generated and provided, rather than only a single realization, for example. Also, in another embodiment, the generation and output of multiple realizations may use one or more native objects to natively perform the transforms or image processing to provide the images or realizations.Type: ApplicationFiled: July 7, 2006Publication date: January 10, 2008Applicant: Microsoft CorporationInventors: Rajat Goel, Margaret L. Goodwin, Radu C. Margarint, Robert A. Wlodarczyk, Thomas W. Olsen, Wei-Chung Jones Wang
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Patent number: 7181480Abstract: A method and system are provided for allowing a user to store image data on a network. The system includes a file uploading component for uploading an image file from each user to the storage system, and for deriving an image metadata set related to the uploaded image file. The system also includes a plurality of database storage facilities for storing each image metadata set. Each database storage facility including at least two logically partitioned sections. The system additionally includes a file management component for managing data storage in order to store each image metadata set in more than one logically partitioned section and in more than one database storage facility, and for directing the image file to an image storage facility.Type: GrantFiled: June 30, 2003Date of Patent: February 20, 2007Assignee: Microsoft CorporationInventors: Mark A. Nikiel, David Byther, Wei-Chung Jones Wang, Michael Culver, Kyung Camillus Paik
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Publication number: 20060248122Abstract: An operating system to componentize file sharing is described, in which a file transport send object is executable on the operating system to designate a shared file for sharing, and in which a notification send object is executable on the operating system to notify of the shared file. An operating system to componentize file sharing is described, in which a file transport receive object is executable on the operating system to receive a shared file, and in which a notification receive object that is executable on the operating system to notify of the shared file.Type: ApplicationFiled: April 27, 2005Publication date: November 2, 2006Applicant: Microsoft CorporationInventors: Mark Nikiel, Ignatius Setiadi, Chun-Kit Chan, Kevin Kim, Shabbir Shahpurwala, Wei-Chung Jones Wang
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Patent number: 7015066Abstract: A method of making a microelectronic assembly buying restraining a substrate in a fixture at room temperature, placing a flip chip on the substrate so that conductive bumps on the flip chip are aligned with contact pads on the substrate, heating the flip chip, the substrate and the fixture to reflow the conductive bumps on the flip chip, cooling the flip chip, substrate and fixture to solidify the conductive bumps and to mount the flip chip to the substrate, depositing an underfill between the flip chip and the substrate, curing the underfill by heating the flip chip, substrate, underfill and fixture to an elevated temperature, and removing the flip chip mounted substrate from the fixture.Type: GrantFiled: September 5, 2001Date of Patent: March 21, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Chender Huang, Jones Wang, Ken Chen
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Patent number: 6960518Abstract: A new method is provided for the interconnection of flip chips to a supporting substrate. The invention starts with a conventional first substrate, that serves as a semiconductor device support structure, over the surface of which a first pattern of contacts points has been provided. The invention then uses a second substrate, for instance a glass or quartz plate, and creates over the surface thereof a second pattern of solder bumps separated by solder non-wettable surfaces. The second pattern is a mirror image of the first pattern. By then overlying the first pattern of contact points with the second pattern of solder bumps, a step of reflow can be applied to the solder bumps, transferring the solder bumps from the second substrate to the contact points provided over the first substrate.Type: GrantFiled: July 19, 2002Date of Patent: November 1, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Chender Huang, Jones Wang, Ken Chen, Hank Huang
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Patent number: 6939789Abstract: The invention includes a method of wafer level chip scale packaging including providing a semiconductor device having a silicon based substrate with discrete devices defined therein and a contact pad near an upper surface thereof, a passivation layer overlying the silicon based substrate and the contact pad, and the passivation layer having an opening therein exposing at least a portion of the contact pad, and a redistribution trace electrically connected to the contact pad near a first end and having a second end of spaced a distance from the contact pad. Forming an encapsulation layer over the semiconductor device including the redistribution trace. Forming an opening in the encapsulation layer down to the redistribution trace. Forming a contact post in the opening in the encapsulation layer, and the contact post having a first end electrically connected to the redistribution trace and a second exposed end.Type: GrantFiled: May 13, 2002Date of Patent: September 6, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chender Huang, Pei-Haw Tsao, Jones Wang, Ken Chen
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Publication number: 20050167807Abstract: A new method is provided for the interface between a stress relieve interface layer of polyimide and a thereover created layer of mold compound. The invention provides for creating a pattern in the stress relieve layer of polyimide before the layer of mold compound is formed over the stress relieve layer of polyimide.Type: ApplicationFiled: February 17, 2005Publication date: August 4, 2005Inventors: Ken Chen, Chender Huang, Pei-Haw Tsao, Jones Wang, Hank Huang
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Patent number: 6884662Abstract: A new method is provided for the interface between a stress relieve interface layer of polyimide and a thereover created layer of mold compound. The invention provides for creating a pattern in the stress relieve layer of polyimide before the layer of mold compound is formed over the stress relieve layer of polyimide.Type: GrantFiled: January 28, 2002Date of Patent: April 26, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ken Chen, Chender Huang, Pei-Haw Tsao, Jones Wang, Hank Huang
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Patent number: 6656827Abstract: A method including providing a first substrate having a first bond pad and a second bond pad; forming a subassembly comprising securing a second substrate to the first substrate with a ground layer interposed between the first substrate and the second substrate; forming a first trench in the subassembly through the first substrate so that the trench is defined at least in part by a side wall of the first substrate and through at least a portion of the ground layer; and forming a first electrically conductive layer overlying the first bond pad, the side wall of the first substrate and overlying a portion of the ground layer.Type: GrantFiled: October 17, 2002Date of Patent: December 2, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Chender Huang, Jones Wang, Ken Chen, Hank Huang
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Publication number: 20030211720Abstract: The invention includes a method of wafer level chip scale packaging including providing a semiconductor device having a silicon based substrate with discrete devices defined therein and a contact pad near an upper surface thereof, a passivation layer overlying the silicon based substrate and the contact pad, and the passivation layer having an opening therein exposing at least a portion of the contact pad, and a redistribution trace electrically connected to the contact pad near a first end and having a second end of spaced a distance from the contact pad. Forming an encapsulation layer over the semiconductor device including the redistribution trace. Forming an opening in the encapsulation layer down to the redistribution trace. Forming a contact post in the opening in the encapsulation layer, and the contact post having a first end electrically connected to the redistribution trace and a second exposed end.Type: ApplicationFiled: May 13, 2002Publication date: November 13, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chender Huang, Pei-Haw Tsao, Jones Wang, Ken Chen
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Patent number: 6638837Abstract: A method of protecting the active surface, front side, of semiconductor wafers during the operations of backside grinding, transporting, and packaging has been achieved. The invention discloses a method for applying an organic passivation layer or an aqueous material for protection of the active components. These materials are easily removed prior to final packaging of the dies.Type: GrantFiled: September 20, 2002Date of Patent: October 28, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Pei-Haw Tsao, Chender Huang, Jones Wang, Ken Chen, Hank Huang
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Publication number: 20030176020Abstract: A new design is provided for the heat spreader of a semiconductor package. Grooves are provided in a surface of the heat spreader, subdividing the heat spreader for purposes of stress distribution into four or more sections. This division of the heat spreader results in a reduction of the mechanical and thermal stress that is introduced by the heat spreader into the device package. Mechanical and heat stress, using conventional heat spreader designs, has a negative, stress induced, effect on the semiconductor die, on the contact points (bump joints) of the semiconductor die and on the solder ball connections of the package.Type: ApplicationFiled: June 3, 2003Publication date: September 18, 2003Inventors: Pei-Haw Tsao, Jones Wang, Ken Chen
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Patent number: 6607942Abstract: A new design is provided for the heat spreader of a semiconductor package. Grooves are provided in a surface of the heat spreader, subdividing the heat spreader for purposes of stress distribution into four or more sections. This division of the heat spreader results in a reduction of the mechanical and thermal stress that is introduced by the heat spreader into the device package. Mechanical and heat stress, using conventional heat spreader designs, has a negative, stress induced, effect on the semiconductor die, on the contact points (bump joints) of the semiconductor die and on the solder ball connections of the package.Type: GrantFiled: July 26, 2001Date of Patent: August 19, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Pei-Haw Tsao, Jones Wang, Ken Chen
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Publication number: 20030045028Abstract: A method of making a microelectronic assembly buying restraining a substrate in a fixture at room temperature, placing a flip chip on the substrate so that conductive bumps on the flip chip are aligned with contact pads on the substrate, heating the flip chip, the substrate and the fixture to reflow the conductive bumps on the flip chip, cooling the flip chip, substrate and fixture to solidify the conductive bumps and to mount the flip chip to the substrate, depositing an underfill between the flip chip and the substrate, curing the underfill by heating the flip chip, substrate, underfill and fixture to an elevated temperature, and removing the flip chip mounted substrate from the fixture.Type: ApplicationFiled: September 5, 2001Publication date: March 6, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Chender Huang, Jones Wang, Ken Chen