Abstract: An alternating phase shift mask. The alternating phase shift mask includes a transparent substrate, a light-shielding layer disposed on the transparent substrate to define a transparent array consisting of a plurality of first phase rows and a plurality of second phase rows alternately interposed between the first phase rows. The alternating phase shift mask further comprises a phase interference enhancement feature disposed a predetermined distance from the outermost row of the transparent array, wherein the phases of the phase interference enhancement feature and the outermost row are reverse.

Abstract: This is related to a method for the manufacture of a capacitor with wing extensions and the capacitor device. The method comprises: (1) causing multiple contact areas to be disposed in alternate positions, such that two adjacent contact areas are complements of each other, (2) depositing electroplating base material (EBM) over the contact area, (3) electroplating a conductive material on the sidewalls of the EBM slab to form plate electrode; and then (4) etching back the EBM leaving only the electrode portion. The capacitor formed by the above method has a larger surface area on the electrode compared with that made by the conventional method, and the cell capacitance is also better. This method is especially effective for the manufacture of high-density memory device.

Abstract: An alternating phase shift mask. The alternating phase shift mask includes a transparent substrate, a light-shielding layer disposed on the transparent substrate to define a transparent array consisting of a plurality of first phase rows and a plurality of second phase rows alternately interposed between the first phase rows. The alternating phase shift mask further comprises a phase interference enhancement feature disposed a predetermined distance from the outermost row of the transparent array, wherein the phases of the phase interference enhancement feature and the outermost row are reverse.

Abstract: This is related to a method for the manufacture of a capacitor with wing extensions and the capacitor device. The method comprises: (1) causing multiple contact areas to be disposed in alternate positions, such that two adjacent contact areas are complements of each other, (2) depositing electroplating base material (EBM) over the contact area, (3) electroplating a conductive material on the sidewalls of the EBM slab to form plate electrode; and then (4) etching back the EBM leaving only the electrode portion. The capacitor formed by the above method has a larger surface area on the electrode compared with that made by the conventional method, and the cell capacitance is also better. This method is especially effective for the manufacture of high-density memory device.

Abstract: A capacitor formed on a conductive plug of a semiconductor substrate has a composite storage node, wherein a Ru conductive layer covers the conductive plug and a conductive oxide layer with a perovskite structure covers the Ru conductive layer. A capacitor dielectric layer covers the composite storage node. An electrode layer covers the capacitor dielectric layer.

Abstract: A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.

Abstract: A method for fabricating semiconductor device is disclosed herein. The first step is to form a first oxide layer on a substrate. Subsequently formed are polycrystalline silicon layer, a polycide layer, optionally a second oxide layer, and a silicon nitride layer on the first oxide layer. A photoresist pattern on the silicon layer is formed thereafter, and the silicon nitride layer is etched using the photoresist pattern as a mask to expose a portion of the polycide layer. The photoresist pattern is then, the polycide layer is isotropically etched to form an under cut in the polycide layer under the etched nitride layer (optional second oxide layer). The width of the top portion of the isotropically etched polycide layer is smaller than the width of the etched nitride layer. The isotropically etched polycide layer is then anistropically etched, and the polycrystalline layer is etched to expose a portion of the first oxide layer to form a multi-layer structure.