Abstract: At least one example embodiment discloses a semiconductor device. The semiconductor device includes a first sense amplifier selectively connected between a first bit line and a second bit line, a second sense amplifier selectively connected between the first bit line and the second bit line, a first power supply circuit configured to provide a power supply voltage to the first sense amplifier in response to a first control signal, a second power supply circuit configured to provide a ground voltage to the second sense amplifier in response to a second control signal, and a switching circuit configured to selectively connect the first power supply circuit with the second power supply circuit in response to a third control signal.

Abstract: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change.

Abstract: At least one example embodiment discloses a semiconductor device. The semiconductor device includes a first sense amplifier selectively connected between a first bit line and a second bit line, a second sense amplifier selectively connected between the first bit line and the second bit line, a first power supply circuit configured to provide a power supply voltage to the first sense amplifier in response to a first control signal, a second power supply circuit configured to provide a ground voltage to the second sense amplifier in response to a second control signal, and a switching circuit configured to selectively connect the first power supply circuit with the second power supply circuit in response to a third control signal.

Abstract: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change.

Abstract: A high speed interface type device can reduce power consumption and a circuit area, and transmit/receive a 4 bit data in one clock period. The high speed interface type device includes a DRAM unit for generating first clock and clock bar signals which do not have a phase difference from a main clock signal, and second clock and clock bar signals having 90° phase difference from the first clock and clock bar signals in a write operation, storing an inputted 4 bit data in one period of the main clock signal according to the first clock to second clock bar signals, synchronizing the stored data with data strobe signals according to the first clock to second clock bar signals in a read operation, and outputting a 4 bit data in one period of the main clock signal, and a controller for transmitting a command, address signal and data signal synchronized with the main clock signal to the DRAM unit in the write operation, and receiving data signals from the DRAM unit in the read operation.

Abstract: A self refresh circuit for a semiconductor memory device can reduce power consumption by varying a self refresh period according to a data holding time of a cell varied by a temperature. The self refresh circuit includes a temperature sensing unit for sensing a temperature, and generating a bias current for adjusting a self refresh period according to a data holding time of a memory cell varied by the temperature, and a ring oscillator unit for generating a pulse signal having a period actively varied according to the temperature by the bias current from the temperature sensing unit.

Abstract: A current mirror type bandgap reference voltage generator which can reduce variations of a reference voltage due to temperature variations, by separately generating a current proportional to an emitter-base voltage and a current proportional to a thermal voltage, and which also can reduce variations of the reference voltage due to variations of a power voltage, by using a current mirror. The current mirror type bandgap reference voltage generator includes: a first current generator for generating a first current proportional to the emitter-base voltage; a second current generator for generating a second current proportional to the thermal voltage; and a reference voltage generator for adding the first and second currents, and generating a constant reference voltage regardless of variations of the temperature and the power voltage. As a result, the constant voltage is generated regardless of variations of the temperature and the power voltage.

Abstract: A current mirror type bandgap reference voltage generator which can reduce variations of a reference voltage due to temperature variations, by separately generating a current proportional to an emitter-base voltage and a current proportional to a thermal voltage, and which also can reduce variations of the reference voltage due to variations of a power voltage, by using a current mirror. The current mirror type bandgap reference voltage generator includes: a first current generator for generating a first current proportional to the emitter-base voltage; a second current generator for generating a second current proportional to the thermal voltage; and a reference voltage generator for adding the first and second currents, and generating a constant reference voltage regardless of variations of the temperature and the power voltage. As a result, the constant voltage is generated regardless of variations of the temperature and the power voltage.

Abstract: A self refresh circuit for a semiconductor memory device can reduce power consumption by varying a self refresh period according to a data holding time of a cell varied by a temperature. The self refresh circuit includes a temperature sensing unit for sensing a temperature, and generating a bias current for adjusting a self refresh period according to a data holding time of a memory cell varied by the temperature, and a ring oscillator unit for generating a pulse signal having a period actively varied according to the temperature by the bias current from the temperature sensing unit.

Abstract: A high speed interface type device can reduce power consumption and a circuit area, and transmit/receive a 4 bit data in one clock period. The high speed interface type device includes a DRAM unit for generating first clock and clock bar signals which do not have a phase difference from a main clock signal, and second clock and clock bar signals having 90° phase difference from the first clock and clock bar signals in a write operation, storing an inputted 4 bit data in one period of the main clock signal according to the first clock to second clock bar signals, synchronizing the stored data with data strobe signals according to the first clock to second clock bar signals in a read operation, and outputting a 4 bit data in one period of the main clock signal, and a controller for transmitting a command, address signal and data signal synchronized with the main clock signal to the DRAM unit in the write operation, and receiving data signals from the DRAM unit in the read operation.