Abstract: Disclosed is a dynamic random access memory (DRAM) device having word line low voltage supply lines for driving word lines in a mesh structure. The DRAM device includes a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix. The memory device further includes regions of sense amplifiers disposed between the cell arrays arranged along the row direction, regions of word line drivers disposed between the cell arrays arranged along the column direction, conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers, and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected for each other at least on the conjunction regions. According to the layout arrangement, loadings of the word line low voltage supply lines are almost equally distributed, and thereby word line low noise are decreased.

Abstract: A layout of a bit line sensing control circuit for a semiconductor memory device includes two bit line pairs extending in a first direction. A power contact is arranged between the two bit line pairs. A power gate is arranged around the power contact. A plurality of sense transistors respectively have a plurality of sense transistor gates. The plurality of sense transistor gates are arranged around the power gate. A pair of control line contacts is arranged in a second direction at an adjacent location outside the two bit line pairs. A control line extends in the second direction and is connected to the power gate through the pair of control line contacts. A power line extends in the second direction adjacent to the control line and is connected to an active area surrounded by the power gate through the power contact.

Abstract: Disclosed is a dynamic random access memory (DRAM) device having word line low voltage supply lines for driving word lines in a mesh structure. The DRAM device includes a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix. The memory device further includes regions of sense amplifiers disposed between the cell arrays arranged along the row direction, regions of word line drivers disposed between the cell arrays arranged along the column direction, conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers, and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected for each other at least on the conjunction regions. According to the layout arrangement, loadings of the word line low voltage supply lines are almost equally distributed, and thereby word line low noise are decreased.