Patents by Inventor Jong-Eun Koo

Jong-Eun Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10289778
    Abstract: A method of simulating an electronic circuit including an N-stage charge pump includes generating a charge pump macro model corresponding to the N-stage charge pump, and simulating the charge pump macro model. The charge pump macro model includes an output terminal, a behavioral block defined by a modeling language, and a passive device block including at least one passive device connected to the output terminal and the behavioral block.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: May 14, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Surojit Sarkar, Jong-Eun Koo
  • Patent number: 9727674
    Abstract: A simulator includes a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delay to synchronize digital and analog signals. The processor includes a delay calculator module for generating one of a rising time and a falling time and a standard delay format (SDF) file using the first netlist, the timing library, and the SPEF file; an SDF file converter module for adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and a digital simulator module for generating an event using a first driving cell according to a compensated interconnect delay description.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Eun Koo, Young Jin Gu, In Youl Lee
  • Publication number: 20160110483
    Abstract: A simulator includes a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delay to synchronize digital and analog signals. The processor includes a delay calculator module for generating one of a rising time and a falling time and a standard delay format (SDF) file using the first netlist, the timing library, and the SPEF file; an SDF file converter module for adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and a digital simulator module for generating an event using a first driving cell according to a compensated interconnect delay description.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 21, 2016
    Inventors: JONG EUN KOO, YOUNG JIN GU, IN YOUL LEE
  • Publication number: 20160034622
    Abstract: A method of simulating an electronic circuit including an N-stage charge pump includes generating a charge pump macro model corresponding to the N-stage charge pump, and simulating the charge pump macro model. The charge pump macro model includes an output terminal, a behavioral block defined by a modeling language, and a passive device block including at least one passive device connected to the output terminal and the behavioral block.
    Type: Application
    Filed: March 25, 2015
    Publication date: February 4, 2016
    Inventors: SUROJIT SARKAR, JONG-EUN KOO
  • Patent number: 9223927
    Abstract: A modeling system includes a processor. The processor includes a capacitor model generator configured to generate a capacitor model based on a received circuit configuration. The capacitor model generator includes an extract module configured to extract parasitic capacitors from the received circuit configuration and a generate module configured to generate the capacitor model. The generate module generates the capacitor model by classifying the parasitic capacitors into a group of coupled capacitors and a group of grounded capacitors; classifying the coupled capacitors into first coupled capacitors and second coupled capacitors according to a corresponding influence on a performance of the circuit; setting the first coupled capacitors to a maintenance state; and converting at least one of the second coupled capacitors into a grounded capacitor, the at least one of the second coupled capacitors being a second coupled capacitor having a capacitance that is below a desired reference value.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: December 29, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jin Gu, Jong-Eun Koo, Kyu-Seok Lee
  • Publication number: 20150154334
    Abstract: A modeling system includes a processor. The processor includes a capacitor model generator configured to generate a capacitor model based on a received circuit configuration. The capacitor model generator includes an extract module configured to extract parasitic capacitors from the received circuit configuration and a generate module configured to generate the capacitor model. The generate module generates the capacitor model by classifying the parasitic capacitors into a group of coupled capacitors and a group of grounded capacitors; classifying the coupled capacitors into first coupled capacitors and second coupled capacitors according to a corresponding influence on a performance of the circuit; setting the first coupled capacitors to a maintenance state; and converting at least one of the second coupled capacitors into a grounded capacitor, the at least one of the second coupled capacitors being a second coupled capacitor having a capacitance that is below a desired reference value.
    Type: Application
    Filed: September 15, 2014
    Publication date: June 4, 2015
    Inventors: Young-Jin GU, Jong-Eun KOO, Kyu-Seok LEE
  • Patent number: 7509596
    Abstract: A power distribution network simulation method capable of speedily and accurately analyzing a large power distribution network. In the power distribution network simulation method, the large original circuit is reduced to a suitable size by using a variable reduction method, a solution of an equation of the reduced circuit is obtained, and a solution of an equation of the original circuit is restored based on the solution of the equation of the reduced circuit by using the variable reduction method. According to the power distribution network simulation method using the variable reduction method, it is possible to speedily and accurately analyze the large power distribution network.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: March 24, 2009
    Assignee: Samsung Electronics Co, Ltd.
    Inventors: Jong-Eun Koo, Kyung-Ho Lee, Young-Hoe Cheon
  • Publication number: 20050203722
    Abstract: A power distribution network simulation method capable of speedily and accurately analyzing a large power distribution network. In the power distribution network simulation method, the large original circuit is reduced to a suitable size by using a variable reduction method, a solution of an equation of the reduced circuit is obtained, and a solution of an equation of the original circuit is restored based on the solution of the equation of the reduced circuit by using the variable reduction method. According to the power distribution network simulation method using the variable reduction method, it is possible to speedily and accurately analyze the large power distribution network.
    Type: Application
    Filed: February 11, 2005
    Publication date: September 15, 2005
    Inventors: Jong-Eun Koo, Kyung-Ho Lee, Young-Hoe Cheon