Patents by Inventor Jong Eun Lee

Jong Eun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250046675
    Abstract: A manufacturing method of a heat dissipation device-integrated heat dissipation substrate for a semiconductor includes a base processing step of preparing a first base plate and a second base plate in the form of metal plates that overlap each other and constitute a part of a metal base, and providing a first base and a second base in which a three-dimensional structure forming the heat media circulation space is formed on an inner surface of at least one of the first base plate and the second base plate, a base coupling step of coupling opposing inner surfaces of the first base and the second base against each other to form heat dissipation device-integrated base, an electrode metal plate preparation step of processing an electrode metal plate to form a groove pattern, and preparing an electrode metal plate configured to cover an area corresponding to at least one circuit unit, and an electrode metal plate bonding step of bonding, via insulating resin, the electrode metal plate to an upper surface of the hea
    Type: Application
    Filed: August 1, 2024
    Publication date: February 6, 2025
    Inventor: Jong Eun LEE
  • Patent number: 12099913
    Abstract: Disclosed herein are a neural-network-lightening method using a repetition-reduction block and an apparatus for the same. The neural-network-lightening method includes stacking (accumulating) an output layer (value) of either one or both of a layer constituting a neural network and a repetition-reduction block in a Condensed Decoding Connection (CDC), and lightening the neural network by reducing a feature map, generated to correspond to data stacked in the CDC, based on a preset reduction layer.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 24, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hye-Jin Kim, Sang-Yun Oh, Jong-Eun Lee
  • Publication number: 20240240140
    Abstract: Disclosed are attenuated Salmonella gallinarum expressing FliC (flagellin) or FliC-hIL2 (human IL2 fused to FliC) and use thereof, wherein the Salmonella strain exhibits excellent immune activation ability and anticancer efficacy and thus can be used as a cancer therapeutic agent, together with or independently from existing anticancer agents.
    Type: Application
    Filed: January 16, 2024
    Publication date: July 18, 2024
    Applicant: ODYSSEUS BIO CO., LTD.
    Inventors: Kwangsoo KIM, Jong-eun Lee, Sol Choy
  • Patent number: 11984326
    Abstract: Provided are a heat dissipating substrate and a preparation method thereof, which can form a precise pattern in a thick electrode metal plate and improve insulating strength and peel strength. heat dissipating substrate for semiconductor may include: an electrode metal plate having a plurality of electrode patterns which are electrically insulated from each other by a pattern space formed therebetween; a metal base disposed under the electrode metal plate, and configured to diffuse heat conducted from the electrode metal plate; an insulating layer formed between the electrode metal plate and the metal base; and an insulating material filled portion configured to fill the pattern space and a peripheral portion outside an electrode pattern group composed of the plurality of electrode patterns, and support the electrode patterns while brought in direct contact with side surfaces of the plurality of electrode patterns.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 14, 2024
    Assignee: IMH INC.
    Inventor: Jong Eun Lee
  • Patent number: 11714727
    Abstract: A stuck-at fault mitigation method for resistive random access memory (ReRAM)-based deep learning accelerators, includes: confirming a distorted output value (Y0) due to a stuck-at fault (SAF) by using a correction data set in a pre-trained deep learning network, by means of ReRAM-based deep learning accelerator hardware; updating an average (?) and a standard deviation (?) of a batch normalization (BN) layer by using the distorted output value (Y0), by means of the ReRAM-based deep learning accelerator hardware; folding the batch normalization (BN) layer in which the average (?) and the standard deviation (?) are updated into a convolution layer or a fully-connected layer, by means of the ReRAM-based deep learning accelerator hardware; and deriving a normal output value (Y1) by using the deep learning network in which the batch normalization (BN) layer is folded, by means of the ReRAM-based deep learning accelerator hardware.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: August 1, 2023
    Assignees: UNIST ACADEMY-INDUSTRY RESEARCH CORPORATION, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Jong Eun Lee, Su Gil Lee, Gi Ju Jung, Mohammed Fouda, Fadi Kurdahi, Ahmed M. Eltawil
  • Publication number: 20220245038
    Abstract: A stuck-at fault mitigation method for resistive random access memory (ReRAM)-based deep learning accelerators, includes: confirming a distorted output value (Y0) due to a stuck-at fault (SAF) by using a correction data set in a pre-trained deep learning network, by means of ReRAM-based deep learning accelerator hardware; updating an average (?) and a standard deviation (?) of a batch normalization (BN) layer by using the distorted output value (Y0), by means of the ReRAM-based deep learning accelerator hardware; folding the batch normalization (BN) layer in which the average (?) and the standard deviation (?) are updated into a convolution layer or a fully-connected layer, by means of the ReRAM-based deep learning accelerator hardware; and deriving a normal output value (Y1) by using the deep learning network in which the batch normalization (BN) layer is folded, by means of the ReRAM-based deep learning accelerator hardware.
    Type: Application
    Filed: January 21, 2022
    Publication date: August 4, 2022
    Applicants: UNIST Academy-Industry Research Corporation, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Jong Eun LEE, Su Gil LEE, Gi Ju JUNG, Mohammed FOUDA, Fadi KURDAHI, Ahmed M. ELTAWIL
  • Publication number: 20220223435
    Abstract: Provided are a heat dissipating substrate and a preparation method thereof, which can form a precise pattern in a thick electrode metal plate and improve insulating strength and peel strength. heat dissipating substrate for semiconductor may include: an electrode metal plate having a plurality of electrode patterns which are electrically insulated from each other by a pattern space formed therebetween; a metal base disposed under the electrode metal plate, and configured to diffuse heat conducted from the electrode metal plate; an insulating layer formed between the electrode metal plate and the metal base; and an insulating material filled portion configured to fill the pattern space and a peripheral portion outside an electrode pattern group composed of the plurality of electrode patterns, and support the electrode patterns while brought in direct contact with side surfaces of the plurality of electrode patterns.
    Type: Application
    Filed: May 29, 2020
    Publication date: July 14, 2022
    Inventor: Jong Eun LEE
  • Patent number: 11131302
    Abstract: A scroll compressor to prevent reverse flow of refrigerant and reducing flow noise. The scroll compressor efficiently distribute refrigerant suctioned into the scroll compressor to a compression chamber and a drive unit. The scroll compressor includes a main body, a fixed scroll fixedly installed in the main body, an orbiting scroll configured to engage with the fixed scroll and perform a relative orbiting motion, and to form a compression chamber with the fixed scroll, a partition plate disposed above the fixed scroll to separate an inside of the main body into a low-pressure portion and a high-pressure portion, a first check valve installed at a discharge port of the fixed scroll to open and close the discharge port, and a second check valve installed on the partition plate to open and close an opening allowing communication between the low-pressure portion and the high-pressure portion.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Kyu Cho, Yang Sun Kim, Jung-Hoon Park, Jong Eun Lee
  • Publication number: 20210131427
    Abstract: Disclosed is a scroll compressor capable of preventing reverse flow of refrigerant and reducing flow noise. The scroll compressor efficiently distribute refrigerant suctioned into the scroll compressor to a compression chamber and a drive unit. The scroll compressor includes a main body, a fixed scroll fixedly installed in the main body, an orbiting scroll configured to engage with the fixed scroll and perform a relative orbiting motion, and to form a compression chamber with the fixed scroll, a partition plate disposed above the fixed scroll to separate an inside of the main body into a low-pressure portion and a high-pressure portion, a first check valve installed at a discharge port of the fixed scroll to open and close the discharge port, and a second check valve installed on the partition plate to open and close an opening allowing communication between the low-pressure portion and the high-pressure portion.
    Type: Application
    Filed: August 29, 2018
    Publication date: May 6, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Kyu CHO, Yang Sun KIM, Jung-Hoon PARK, Jong Eun LEE
  • Publication number: 20200175353
    Abstract: Disclosed herein are a neural-network-lightening method using a repetition-reduction block and an apparatus for the same. The neural-network-lightening method includes stacking (accumulating) an output layer (value) of either one or both of a layer constituting a neural network and a repetition-reduction block in a Condensed Decoding Connection (CDC), and lightening the neural network by reducing a feature map, generated to correspond to data stacked in the CDC, based on a preset reduction layer.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 4, 2020
    Inventors: Hye-Jin KIM, Sang-Yun OH, Jong-Eun LEE
  • Publication number: 20170124401
    Abstract: A system and method for searching for a position of an object are provided. The system includes an image matching unit configured to extract a path from a map indicating a target region, and match a node present in the path and a captured image obtained by a capturing device installed at a position corresponding to the node; a path synthesis unit configured to synthesize the path in the captured image; and an object search unit configured to receive an estimated path of a target object and information related to an exposure direction in an image from a user, and select one or more among a plurality of capturing devices installed in the target region using the received information and the captured image.
    Type: Application
    Filed: December 28, 2015
    Publication date: May 4, 2017
    Applicant: SAMSUNG SDS CO., LTD.
    Inventors: Sung-Hoon CHOI, Jong-Eun LEE, Ju-Dong KIM
  • Patent number: 9429144
    Abstract: An electricity-generating system using solar heat energy comprises: a heat storage tank, a pair of heat-sensitizing units with valves, a steam turbine, a solar collecting system comprising a fixed body in the form of a mesh net having mesh openings, a condenser lens coupled to each of the mesh openings of the fixed body, a condenser unit installed at the bottom portion of the fixed body, which includes a collector lens that increases the concentration of energy focused through the condenser lens and transfers heat to the bottom of the body thereof; a heat storage tank combined with the bottom portion of the fixed body, which heats and stores the heat storage medium by heat energy transferred through the collector lens; a circulation conduit which has an upper plate-shaped coiled tube and a lower coiled circulation tube, which is stacked and contained in the heat storage tank.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: August 30, 2016
    Inventor: Jong Eun Lee
  • Publication number: 20150242308
    Abstract: Provided is a memory device including a logic layer including at least one of a peripheral device, an interface, and a built-in self-test (BIST) module and a reconfigurable accelerator (RA), and at least one data layer to store data, wherein the RA is positioned in a vacant space of the logic layer and processes at least a portion of a task processed by the memory device.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 27, 2015
    Inventors: Yong Joo KIM, Jin Yong LEE, Yun Heung PAEK, Jong Eun LEE
  • Publication number: 20150033739
    Abstract: Disclosed is an electricity-generating system using solar heat energy. The electricity-generating system concentrates solar heat during the daylight hours through a condenser lens at a collector lens, heats a heat storage medium and steam in a latent heat state through the collector lens so as to produce a sensible heat state, drives a generator using the discharge of steam pressure, and in the remaining time, heats the latent heat steam in a heat storage tank in which the heat storage medium is contained so as to drive the generator and generate electricity.
    Type: Application
    Filed: November 14, 2012
    Publication date: February 5, 2015
    Inventor: Jong Eun Lee
  • Publication number: 20140191397
    Abstract: A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.
    Type: Application
    Filed: March 12, 2014
    Publication date: July 10, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Gyu KANG, Ho-Tae JIN, Tae-ho MOON, Il-Soo CHOI, Jong-Eun LEE
  • Patent number: 8698311
    Abstract: A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Gyu Kang, Ho-Tae Jin, Tae-ho Moon, Il-soo Choi, Jong-Eun Lee
  • Publication number: 20130201768
    Abstract: An internal voltage generating circuit and a semiconductor memory device including the internal voltage generating circuit are disclosed. The internal voltage generating circuit includes a first voltage generating circuit, a second voltage generating circuit, and a third voltage generating circuit. The first voltage generating circuit stabilizes a first external supply voltage to generate a first internal voltage. The second voltage generating circuit stabilizes the first external supply voltage and a second external supply voltage to generate a second internal voltage having a voltage level higher than the first internal voltage. The third voltage generating circuit stabilizes the second internal voltage to generate a third internal voltage having a voltage level lower than the second internal voltage. Accordingly, the semiconductor memory device may be insensitive to a change in an external supply voltage and have small power consumption.
    Type: Application
    Filed: September 7, 2012
    Publication date: August 8, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hee KANG, Jong-Eun LEE, Dong-Su LEE
  • Publication number: 20130069229
    Abstract: A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 21, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Gyu KANG, Ho-Tae JIN, Tae-ho MOON, Il-soo CHOI, Jong-Eun LEE
  • Publication number: 20130023442
    Abstract: Single nucleotide polymorphisms (SNP) for predicting recurrence of hepatocellular carcinoma after curative surgical resection are provided. The SNPs have a significant correlation with higher risk of hepatocellular carcinoma recurrence after curative surgical resection. Therefore, the SNPs can be used in developing micro-arrays or test kits for predicting recurrence of hepatocellular carcinoma, and in screening drugs to prevent recurrence of hepatocellular carcinoma after curative surgical resection.
    Type: Application
    Filed: March 22, 2011
    Publication date: January 24, 2013
    Inventors: Young Hwa Chung, Eun Sil Yu, Young-Joo Lee, Jeong A. Kim, Jong-Eun Lee
  • Publication number: 20130017975
    Abstract: Single nucleotide polymorphisms (SNP) for predicting prognosis of hepatocellular carcinoma after curative surgical resection are provided. The SNPs have a significant correlation with an over-expression of MTA1 which is useful prognostic factor for prediction of prognosis or poor survival after curative surgical resection of hepatocellular carcinoma. Therefore, the SNPs can be used in developing micro-arrays or test kits for prediction of the prognosis of hepatocellular carcinoma, and in screening drugs to improve poor prognosis of hepatocellular carcinoma after curative surgical resection.
    Type: Application
    Filed: March 22, 2011
    Publication date: January 17, 2013
    Applicant: University of Ulsan Foundation For Industry Cooperation
    Inventors: Young Hwa Chung, Neung Hwa Park, Eun Sil Yu, Young-Joo Lee, Jeong A Kim, Dan-Bi Lee, Sae-Hwan Lee, Jong-Eun Lee