Abstract: A current control circuit for a dynamic random access memory device which has a bit line sense amplifier for sensing and amplifying bit data on a bit line, and a data bit clamping circuit for supplying current to the bit line sense amplifier. The current control circuit is adapted to control the current from the data bit clamping circuit to the bit line sense amplifier. The current control circuit comprises a first path switching circuit for forming a current path from the data bit clamping circuit to the bit line sense amplifier during a refresh operation, a second path switching circuit connected between the first path switching circuit and the data bit clamping circuit, for opening/closing the current path, and a path controller for generating a current control signal in response to an address signal and supplying the generated current control signal to the second path switching circuit.

Abstract: A bootstrap circuit comprising a capacitive device connected between an input line and an output line to boost a signal from the input line, a first voltage supply path being selectively driven in response to a voltage on the output line to transfer or block a supply voltage from a supply voltage source to the output line, a second voltage supply path connected in parallel to the first voltage supply path to transfer or block the supply voltage from the supply voltage source to the output line, and a controller for controlling the second voltage supply path in response to the signal from the input line. According to the present invention, the bootstrap circuit enhances a response speed of an output signal with respect to an input signal. Therefore, the bootstrap circuit can boost the input signal stably and accurately regardless of an impulse noise component.

Abstract: A column redundancy device for a semiconductor memory comprising a first fuse box for determining in response to a first row address signal whether a desired number of a plurality of cell array blocks are selected, a second fuse box for determining in response to a second row address signal and a first column address signal and an output signal from the first fuse box whether any one of the desired number of cell array blocks is selected, and a third fuse box for determining in response to a second column address signal and an output signal from the second fuse box whether any one of bit lines in the cell array block selected by one of the second row address signal and the first column address signal and the first row address signal is addressed and selectively driving any one of memory cells included in a redundancy cell array in accordance with the determined result.

Abstract: A redundancy enable circuit of a semiconductor memory device, including an address input unit provided with a plurality of repair fuses and a plurality of pass transistors for respectively receiving address signals necessary and unnecessary for a refresh option, the address input unit allowing the necessary ones of the of the address signals to be inputted respectively at corresponding ones of the pass transistors and thereby to control the signal-received pass transistors while preventing the unnecessary ones of the address signals from being inputted respectively at corresponding ones of the pass transistors, whereby an increased repair efficiency is obtained.