Patents by Inventor Jong Gon Heo

Jong Gon Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8999825
    Abstract: This invention relates to a method of healing defects at junctions of a semiconductor device, which includes growing a p-Ge layer on a substrate, performing ion implantation on the p-Ge layer to form an n+ Ge region or performing in-situ doping on the p-Ge layer and then etching to form an n+ Ge region or depositing an oxide film on the p-Ge layer and performing patterning, etching and in-situ doping to form an n+ Ge layer, forming a capping oxide film, performing annealing at 600˜700° C. for 1˜3 hr, and depositing an electrode, and in which annealing enables Ge defects at n+/p junctions to be healed and the depth of junctions to be comparatively reduced, thus minimizing leakage current, thereby improving properties of the semiconductor device and achieving high integration and fineness of the semiconductor device.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: April 7, 2015
    Assignees: Korea Advanced Nano Fab Center, Sungkyunkwan University Research & Business Foundation
    Inventors: Won Kyu Park, Jong Gon Heo, Dong Hwan Jun, Jin Hong Park, Jae Woo Shim
  • Publication number: 20140187021
    Abstract: This invention relates to a method of healing defects at junctions of a semiconductor device, which includes growing a p-Ge layer on a substrate, performing ion implantation on the p-Ge layer to form an n+ Ge region or performing in-situ doping on the p-Ge layer and then etching to form an n+ Ge region or depositing an oxide film on the p-Ge layer and performing patterning, etching and in-situ doping to form an n+ Ge layer, forming a capping oxide film, performing annealing at 600˜700° C. for 1˜3 hr, and depositing an electrode, and in which annealing enables Ge defects at n+/p junctions to be healed and the depth of junctions to be comparatively reduced, thus minimizing leakage current, thereby improving properties of the semiconductor device and achieving high integration and fineness of the semiconductor device.
    Type: Application
    Filed: November 21, 2013
    Publication date: July 3, 2014
    Applicant: Korea Advanced Nano Fab Center
    Inventors: Won Kyu Park, Jong Gon Heo, Dong Hwan Jun, Jin Hong Park, Jae Woo Shim