Abstract: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.

Abstract: A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is

Abstract: A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is

Abstract: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.

Abstract: In a method for planarizing an insulation layer in a semiconductor device, an insulation layer is formed over a semiconductor substrate having a cell region and a peripheral region. The cell region is higher than the peripheral region due to a capacitor formed in the cell region. A metal layer is formed over the insulation layer. The metal layer is chemical mechanical polished to expose the insulation layer portion in the cell region. The exposed insulation layer portion in the cell region is chemical mechanical polishing to planarize the insulation layer, and the planarized insulation layer and the remaining metal layer are chemical mechanical polishing to remove the metal layer remained in the peripheral region. The method for planarizing an insulation layer does not require a separate photosensitive layer forming process or a dry etching process.

Abstract: Disclosed herein are a CMP slurry composition with high-planarity and a CMP process for polishing a dielectric film using the same. More specifically, a CMP slurry composition with high-planarity includes a carbon compound having tens of thousands of carboxyl groups and having a molecular weight ranging from hundreds of thousands to millions, an abrasive, and water. A CMP process for polishing a dielectric film utilizes the disclosed slurry composition. The slurry composition enables complete and overall planarization of the dielectric film by polishing the part of the film having a higher step difference through CMP process. Accordingly, the disclosed slurry composition is useful for the CMP process of all semiconductor devices including those having ultrafine patterns.

Abstract: Disclosed is a method for detecting an end-point of a CMP process of a semiconductor device. More specifically, when all polishing processes are performed using a nitride film as a polishing barrier film, a buffer layer including nitrogen is formed on the nitride film and a polishing process is performed. Then, the concentration of NO from ammonia gas generated from the buffer layer is detected so that the nitride film may be polished to a desired target without damage of the nitride film. As a result, an end-point can be set.

Abstract: The present invention discloses method for manufacturing device isolation film wherein a high selectivity slurry containing MxPyOz is used for polishing nitride film to prevent the generation of moat. In accordance with the method, a pad oxide film and a pad nitride film formed on a semiconductor substrate and the semiconductor substrate are etched to form a trench. A liner nitride film and an oxide film for device isolation film filling the trench are formed on the entire surface. The oxide film for device isolation film is first etched using a low selectivity slurry, and further etched using a high selectivity slurry to expose the liner nitride film. The liner nitride film is polished using a high selectivity slurry containing MxPyOz and the pad nitride film is then removed.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device. The method comprises the steps of: forming a nitride film for storage electrode on a semiconductor substrate; forming an oxide film for storage electrode on the nitride film; selectively etching the oxide film and the nitride film to define a storage electrode region; forming a conductive layer for storage electrode on the semiconductor substrate including the storage electrode region; forming a gap-filling nitride film on the semiconductor substrate to fill up the storage electrode region; performing a CMP process using the oxide film as a polishing stop layer to form a storage electrode; and removing the gap-filling nitride film.

Abstract: CMP slurries for oxide film and a method for forming a metal line contact plug of a semiconductor device are described herein. When a polishing process of a multi-layer film is performed by using the disclosed CMP slurry for oxide film including an HXOn compound (wherein n is an integer from 1 to 4), a stable landing plug poly can be formed by preventing step differences by reducing interlayer polishing speed differences.

Abstract: A method for manufacturing of a metal line contact plug of a semiconductor device by performing a two step CMP process using (1) a first slurry solution having high etching selectivity of metal/insulating film and (2) a second slurry solution having small etching selectivity of metal/insulating film, thereby minimizing dependency on CMP devices and separating easily a metal line contact plug.

Abstract: A CMP slurry for a semiconductor device and a method for manufacturing the semiconductor device using the same, more specifically, a slurry including an additive having high affinity to a nitride film, and a method for polishing a complex film consisting of a polysilicon film and an oxide film or an oxide film using the same are described herein. When the complex film consisting of the polysilicon film and the oxide film removed by using the CMP slurry, a hard mask film which is the nitride film is not removed. Therefore, a polysilicon plug of the semiconductor device can be formed without exposing a word line electrode. In addition, when the oxide film is removed by using the CMP slurry, the slurry includes Al or SiO2 having spherical shaped particles as an abrasive, to form an STI type device isolation film which does not have scratches.

Abstract: The present invention discloses methods for fabricating a semiconductor device. In one embodiment, a conductive interconnection is formed on a semiconductor substrate to overlap with a mask insulating film pattern. An insulating film spacer is formed at side walls of the pattern, a high temperature oxide layer is formed on the resultant structure, and an interlayer insulating film is formed on the HTO film to planarize the surface of the resultant structure. Storage electrode and bit line contact holes are formed to expose the semiconductor substrate, by etching the interlayer insulating film according to a photolithography process using a contact mask. A landing plug poly is formed by depositing a conductive layer for a contact plug to fill up the contact holes.

Abstract: CMP slurries for oxide film and a method for forming a metal line contact plug of a semiconductor device are described herein. When a polishing process of a multi-layer film is performed by using the disclosed CMP slurry for oxide film including an HXOn compound (wherein n is an integer from 1 to 4), a stable landing plug poly can be formed by preventing step differences by reducing interlayer polishing speed differences.

Abstract: A method for manufacturing a metal line contact plug of a semiconductor device is disclosed. A stable landing plug poly is formed by etching an interlayer insulating film by using a CMP (chemical mechanical polishing) slurry for an oxide film that includes an alkyl ammonium salt having a high affinity to the oxide film without damaging the hard mask nitride film.

Abstract: A chemical mechanical polishing (hereinafter, referred to as ‘CMP’) slurry for metal is disclosed, more specifically, method for manufacturing metal line contact plug of semiconductor device using an acidic CMP slurry for oxide film further comprising an oxidizer and a complexing agent, which polishes a metal, an oxide film and a nitride film at a similar speed, thereby easily separates a metal line contact plug.

Abstract: A method for manufacturing of a metal line contact plug of a semiconductor device by performing a two step CMP process using (1) a first slurry solution having high etching selectivity of metal/insulating film and (2) a second slurry solution having small etching selectivity of metal/insulating film, thereby minimizing dependency on CMP devices and separating easily a metal line contact plug.

Abstract: The present invention discloses methods for fabricating a semiconductor device. In one embodiment, a conductive interconnection is formed on a semiconductor substrate to overlap with a mask insulating film pattern. An insulating film spacer is formed at side walls of the pattern, a high temperature oxide layer is formed on the resultant structure, and an interlayer insulating film is formed on the HTO film to planarize the surface of the resultant structure. Storage electrode and bit line contact holes are formed to expose the semiconductor substrate, by etching the interlayer insulating film according to a photolithography process using a contact mask. A landing plug poly is formed by depositing a conductive layer for a contact plug to fill up the contact holes.