Abstract: A register or memory control circuit for selecting registers using a reduced number of address lines. The register control circuit partitions registers into blocks and utilizes a decoder and an index register to select individual registers. An additional decoder may be used in conjunction with the index register in order to further increase the number of registers which may be selected by the register control circuit. The index register provides index data signals on "n" output lines. Each of the "n" index register output lines is connected to a corresponding one of "n" register blocks, so that the "n" output lines of the index register and (n- 1) output lines of the decoder can address (n- 1)n registers.