Abstract: A hot carrier protection circuit comprises two transistors of the same size which are serially arranged and a third transistor for precharging a node which connects the other two transistors. The third transistor has its source coupled to the source of one of the two transistors, a drain coupled to the drain of the same transistor while its gate is coupled to a power source Vcc.

Abstract: A word line driving circuit for a DRAM comprises, a number of CMOS type word line driving stages, a voltage level shifter and a negative transferrer connected between the voltage level shifter and a common gate electrode node of the CMOS type word line driving stages, for applying a voltage signal varying from a driving voltage to a negative voltage below ground potential to the common gate electrode node.

Abstract: An undershoot resisting input circuit for a semi-conductor device having a first terminal for a power supply, a second terminal for an external input, and an internal holding node in the semiconductor device, comprising a p-channel MOSFET having a gate connected to receive an address input signal and a source connected to the first terminal, a first n-channel MOSFET having a gate connected to receive the address input signal, a drain connected to the drain of the p-channel MOSFET and a source connected to the second terminal, a second n-channel MOSFET having a gate connected to the drain of the p-channel MOSFET and a drain connected to the second terminal, an inverter for inverting the address input signal, and a third n-channel MOSFET having a gate connected to an output terminal of the inverter, a drain connected to the source of the second n-channel MOSFET and a source connected to the internal holding node.

Abstract: An address input buffer circuit for a semi-conductor storage device, comprising an input circuit 62 being controlled by an external input address signal An, an internal reference voltage signal Vref and a setup enable signal .phi.AXE; a setup circuit 63 connected to both stages of said input circuit 62; a sense amplifying circuit 61 connected to both stages of said setup circuit 63; a pair of charging circuits 67 and 68 connected to said both stages of said setup circuit 63 respectively and to a power source; a pair of hold circuits 64 and 65 connected to said both stages of said setup circuit 63 respectively; a drive circuit 66 connected to said sense amplifying circuit 61; and an output circuit 71 connected to said pair of hold circuits 64 and 65.

Abstract: The present invention provides an architecture of a DRAM cell array having a plurality of bit lines and word lines. The word lines are formed by arranging metal word lines on poly-silicon word lines in parallel, and two bit lines construct a column. The metal word lines and the poly-silicon word lines are contacted to each other every predetermined column. The contacts form metal shunted areas of word lines in a high bit density semiconductor device. In the present invention, the two bit lines that are located in the vicinity of metal shunted area are conjoined together in order to construct a column, and the column is connected to a bit line sense amplifier.

Abstract: The invention relates to a low power redundancy circuit used in memory device and comprises operation control fuse circuit 47, an OR gate 48, a switching circuit 56, a fuse circuit 45, and a latch-back circuit 57. The latch-back circuit 57 is composed of p channel MOSFET 53 and inverters.

Abstract: A high voltage generating circuit for semi-conductor devices which removes a threshold voltage and generates a high voltage above a source voltage or a negative voltage below a ground voltage, comprising an oscillation signal generating circuit, clamping circuits 51 and 52 and charge pump circuits 53 and 54, for inputting first to fourth oscillation signals from said oscillation signal generating means, and a charge transfer circuit 55. Also, the high voltage generating circuit according to the present invention comprises an initial state control circuit 56 for controlling an initial state of a final output stage Vpp. The present high voltage generating circuit removes a threshold voltage loss in clamping and charge transfer devices to increase an efficiency of the semi-conductor device. Therefore, a sufficient high voltage above the source voltage can be used to prevent a malfunction of the semi-conductor device.

Abstract: A latching circuit for sense amplifier in a DRAM for gradually decrease the potential level at the latching point, that is, .phi.S node of N-channel sense amplifying unit of the sense amplifier from the potential level which is lower than that of bit line charging voltage to the potential level of the ground, when a sensing operation of the sense amplifier is enabled, is disclosed. The latching circuit for sense amplifier further comprises a Schmitt trigger circuit for preventing the previous enabling of the sensing operation of the sense amplifier from occurring before data signal from the selected memory cell of the memory cell array apparatus in the DRAM is transferred to 0-bit line B0. A DRAM comprising the latching circuit for sense amplifier and the Schmitt trigger circuit, is also disclosed.

Abstract: A sense amplifier for sensing and amplifying data existing at a pair of bit lines in a DRAM and having double power lines for supplying separate supply voltages to a P-channel sense amplifying unit and to an N-channel sense amplifying unit in a partially activatable DRAM and comprising a memory cell array apparatus having a pair of bit lines BL and BL is disclosed whereby a peak current occurrence in the partially activatable DRAM is prevented and the sensing ability of the sense amplifier is increased.

Abstract: Quinolone compounds of the general formula ##STR1## pharmaceutical compositions active against bacterial infections containing such compounds, processes for the manufacture of the quinolone compounds and the compositions and the use of the quinolone compounds for the manufacture of pharmaceutical compositions for the treatment of bacterial infections.

Abstract: Diazabicycloamine compounds of the general formula I and their acid salts ##STR1## wherein m represents an integer of 1 to 3,n represents 1 or 2, andR.sub.1 or R.sub.2 represents hydrogen or lower alkyl group, a process for their manufacture and their use for the preparation of novel quinolone compounds having excellent antibacterial activity.

Abstract: A bootstrapping level control circuit for use in a word line signal producing circuit in a DRAM is disclosed. The bootstrapping level control circuit detects an existing potential level at a word line signal source and provides variable bootstrapping efficiency according to the detected existing potential level at the word line signal source to supply sufficient supply voltage Vcc of the word line signal source to a memory cell array apparatus and to thereby prevent double bootstrapping effects from occurring in a word line signal transferring control circuit. The bootstrapping level control circuit further comprises a Vcc level detector for detecting the existing potential level at the word line signal source. The Vcc level detector includes a first, second and a third Vcc level detecting circuits with each Vcc level detecting circuit having a predetermined inverting level, respectively, being different relative to each other.

Abstract: A separation circuit for a DRAM where the separation circuit comprises a first separation circuit and a second separation circuit is disclosed. The first separation circuit and the second separation circuit includes a high resistive MOSFET Q7, MOSFET Q9 and a low resistive MOSFET Q8, MOSFET Q10, respectively. The circuit enables the rapid transfer of data during the reading and writing of data to and from a selected memory cell without signal loss which results in an increased sensing ability of a sense amplifier.