Abstract: An electronic device includes a connector connected to a cable external to the electronic device and including a plurality of pins; a first water detection circuit connected to at least one first pin of the plurality of pins and generating a first detection result by detecting whether there is water in the connector based on resistance of the at least one first pin; and a second water detection circuit connected to at least one second pin of the plurality of pins, entering a water detection mode when the first detection result indicates the presence of water, and detecting whether there is water in the connector based on resistance of the at least one second pin.

Abstract: An electronic device includes a connector connected to a cable external to the electronic device and including a plurality of pins; a first water detection circuit connected to at least one first pin of the plurality of pins and generating a first detection result by detecting whether there is water in the connector based on resistance of the at least one first pin; and a second water detection circuit connected to at least one second pin of the plurality of pins, entering a water detection mode when the first detection result indicates the presence of water, and detecting whether there is water in the connector based on resistance of the at least one second pin.

Abstract: A power amplifier circuit including a power transistor unit generating an output signal based on a predetermined pulse-width modulated signal. The power transistor unit includes a plurality of transistors and a delay circuit unit. The delay circuit unit sequentially drives the plurality of transistors with a predetermined time delay based on the pulse-width modulated signal.

Abstract: A pulse width modulation (PWM) modulator includes an integrator generating an integrated signal based on an input signal and an output signal, a low pass filter (LPF) receiving the integrated signal and performing low pass filtering, a comparator receiving an output signal of the LPF and a predetermined reference signal, comparing the received signals, and outputting a PWM signal, a dead time setup block outputting a first signal and a second signal having a predetermined phase difference therebetween based on the PWM signal, and a power stage buffering the first and second signals and generating the output signal based on a result of buffering. In the PWM modulator and a class-D amplifier having the PWM modulator, EMI can be reduced.

Abstract: Pulse-width modulation (PWM) circuits and methods integrate a feedback signal and an input signal to generate an integral signal, and generate a PWM signal by switching an output node from a first source voltage to a second source voltage based upon comparing the integral signal with a first reference voltage, and switching the output node from the second source voltage to the first source voltage based upon comparing the integral signal with a second reference voltage. A comparator unit compares the integral signal with the first and second reference (threshold) voltages, and a drive circuit for buffering the comparator unit's output signals generates drive signals. A feedback circuit generates the feedback signal based on (e.g., proportional with) the PWM signal. The switching circuit may include a P-type switch (e.g., PMOS transistor) and a N-type switch (e.g., NMOS transistor). Associated class-D audio amplifiers and modulation methods are provided.

Abstract: A modulation system and method having a high linearity. The system is a PWM modulator or a class D amplifier and includes an integrator, a low pass filter (LPF), a comparator, and an output circuit. The LPF is located before the comparator. Jitter noise produced by the comparator and/or switching noise of the output circuit are removed by feedback to the input. Thus, the linearity of the modulation system is provided.

Abstract: A pulse width modulation (PWM) modulator includes an integrator generating an integrated signal based on an input signal and an output signal, a low pass filter (LPF) receiving the integrated signal and performing low pass filtering, a comparator receiving an output signal of the LPF and a predetermined reference signal, comparing the received signals, and outputting a PWM signal, a dead time setup block outputting a first signal and a second signal having a predetermined phase difference therebetween based on the PWM signal, and a power stage buffering the first and second signals and generating the output signal based on a result of buffering. In the PWM modulator and a class-D amplifier having the PWM modulator, EMI can be reduced.

Abstract: A power amplifier circuit including a power transistor unit generating an output signal based on a predetermined pulse-width modulated signal. The power transistor unit includes a plurality of transistors and a delay circuit unit. The delay circuit unit sequentially drives the plurality of transistors with a predetermined time delay based on the pulse-width modulated signal.

Abstract: A pulse width modulation (PWM) circuit comprising an input circuit, first and second controllers, and first and second Schmidt triggers. The first controller sets a first voltage level by a first current generated responding to an input signal and an output of the input circuit. The first Schmidt trigger sets a first logic level when an output of the first controller reaches the first voltage level. The second controller sets a second voltage level by a second current generated responding to the input signal and an output of the first Schmidt trigger. The second Schmidt trigger generates a PWM output signal with a variable frequency in accordance with the first and second currents.

Abstract: Pulse-width modulation (PWM) circuits and methods integrate a feedback signal and an input signal to generate an integral signal, and generate a PWM signal by switching an output node from a first source voltage to a second source voltage based upon comparing the integral signal with a first reference voltage, and switching the output node from the second source voltage to the first source voltage based upon comparing the integral signal with a second reference voltage. A comparator unit compares the integral signal with the first and second reference (threshold) voltages, and a drive circuit for buffering the comparator unit's output signals generates drive signals. A feedback circuit generates the feedback signal based on (e.g., proportional with) the PWM signal. The switching circuit may include a P-type switch (e.g., PMOS transistor) and a N-type switch (e.g., NMOS transistor). Associated class-D audio amplifiers and modulation methods are provided.

Abstract: A pulse width modulation (PWM) circuit comprising an input circuit, first and second controllers, and first and second Schmidt triggers. The first controller sets a first voltage level by a first current generated responding to an input signal and an output of the input circuit. The first Schmidt trigger sets a first logic level when an output of the first controller reaches the first voltage level. The second controller sets a second voltage level by a second current generated responding to the input signal and an output of the first Schmidt trigger. The second Schmidt trigger generates a PWM output signal with a variable frequency in accordance with the first and second currents.

Abstract: A pulse width modulation (PWM) circuit comprising an input circuit, first and second controllers, and first and second Schmidt triggers. The first controller sets a first voltage level by a first current generated responding to an input signal and an output of the input circuit. The first Schmidt trigger sets a first logic level when an output of the first controller reaches the first voltage level. The second controller sets a second voltage level by a second current generated responding to the input signal and an output of the first Schmidt trigger. The second Schmidt trigger generates a PWM output signal with a variable frequency in accordance with the first and second currents.

Abstract: A PLL circuit includes a control circuit for generating a reference control signal. A reception divider, reference divider, and transmission divider respectively divide an output signal of a receiver VCO according to a reception division data signal, an output signal of a crystal oscillator according to a reference division data signal, and an output signal of a transmitter VCO according to a transmission division data signal. A first and second phase detector respectively detect frequency and phase differences between a reception divider output and a reference divider output and between a transmission divider output and the reference divider output.

Abstract: A pulse width modulation (PWM) circuit comprising an input circuit, first and second controllers, and first and second Schmidt triggers. The first controller sets a first voltage level by a first current generated responding to an input signal and an output of the input circuit. The first Schmidt trigger sets a first logic level when an output of the first controller reaches the first voltage level. The second controller sets a second voltage level by a second current generated responding to the input signal and an output of the first Schmidt trigger. The second Schmidt trigger generates a PWM output signal with a variable frequency in accordance with the first and second currents.

Abstract: A PLL circuit includes a control circuit for generating a reference control signal. A reception divider, reference divider, and transmission divider respectively divide an output signal of a receiver VCO according to a reception division data signal, an output signal of a crystal oscillator according to a reference division data signal, and an output signal of a transmitter VCO according to a transmission division data signal. A first and second phase detector respectively detect frequency and phase differences between a reception divider output and a reference divider output and between a transmission divider output and the reference divider output.