Patents by Inventor Jong-Heui Song
Jong-Heui Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8372198Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: GrantFiled: March 6, 2008Date of Patent: February 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Patent number: 8039345Abstract: A method of forming a semiconductor device may include forming a first pattern on a substrate, and forming a first dielectric layer on the first pattern. The first pattern may be between portions of the first dielectric layer and the substrate. A second dielectric layer may be formed on the first dielectric layer, and the first dielectric layer may be between the first pattern and the second dielectric layer. A second pattern may be formed on the second dielectric layer. Portions of the second dielectric layer may be exposed by the second pattern, and the first and second dielectric layers may be between portions of the first and second patterns. The exposed portions of the second dielectric layer may be isotropically etched.Type: GrantFiled: June 16, 2010Date of Patent: October 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-yub Jeon, Jong-heui Song, Song-yi Yang
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Patent number: 8003487Abstract: In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.Type: GrantFiled: December 16, 2008Date of Patent: August 23, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Du-Hyun Cho, Jong-Heui Song, Sang-Sup Jeong, Tae-Woo Kang, Seung-Joo Yoo
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Publication number: 20110059602Abstract: A method of forming a semiconductor device may include forming a first pattern on a substrate, and forming a first dielectric layer on the first pattern. The first pattern may be between portions of the first dielectric layer and the substrate. A second dielectric layer may be formed on the first dielectric layer, and the first dielectric layer may be between the first pattern and the second dielectric layer. A second pattern may be formed on the second dielectric layer. Portions of the second dielectric layer may be exposed by the second pattern, and the first and second dielectric layers may be between portions of the first and second patterns. The exposed portions of the second dielectric layer may be isotropically etched.Type: ApplicationFiled: June 16, 2010Publication date: March 10, 2011Inventors: Kyung-yub Jeon, Jong-heui Song, Song-yi Yang
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Patent number: 7745290Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.Type: GrantFiled: July 3, 2007Date of Patent: June 29, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Seo, Jong-Heui Song, Jae-Seung Hwang, Min-Chul Chae, Woo-Jin Cho, Yun-Seung Kang, Young-Mi Lee
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Patent number: 7667221Abstract: In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.Type: GrantFiled: February 21, 2007Date of Patent: February 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Heui Song, Yong-Sun Ko, Jae-Seung Hwang, Jun Seo
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Publication number: 20090162989Abstract: In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.Type: ApplicationFiled: December 16, 2008Publication date: June 25, 2009Inventors: Du-Hyun Cho, Jong-Heui Song, Sang-Sup Jeong, Tae-Woo Kang, Seung-Joo Yoo
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Patent number: 7531414Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.Type: GrantFiled: December 13, 2007Date of Patent: May 12, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Chul Park, Jun Seo, Tae-Hyuk Ahn, Hyuk-Jin Kwon, Jong-Heui Song, Dae-Keun Kang
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Publication number: 20090117723Abstract: In a method of forming a conductive pattern in a semiconductor device, a conductive layer including a metal is formed on a substrate. A mask including carbon is provided on the conductive layer, and the conductive pattern is formed on the substrate by etching the conductive layer using the mask as an etching mask. The mask is removed from the conductive pattern by an oxygen plasma ashing process. An oxidized portion of the conductive pattern is reduced. The conductive pattern may have a desired resistance by reducing the oxidized portion to improve electrical characteristics and reliability of the semiconductor device.Type: ApplicationFiled: October 15, 2008Publication date: May 7, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-Kyu Kim, Bum-Soo Kim, Jong-Heui Song, Sang-Sup Jeong, Sung-Gil Choi, Kuk-Han Yoon
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Publication number: 20080149021Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: ApplicationFiled: March 6, 2008Publication date: June 26, 2008Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Publication number: 20080152866Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: ApplicationFiled: March 6, 2008Publication date: June 26, 2008Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Publication number: 20080124871Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.Type: ApplicationFiled: July 3, 2007Publication date: May 29, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun SEO, Jong-Heui SONG, Jae-Seung HWANG, Min-Chul CHAE, Woo-Jin CHO, Yun-Seung KANG, Young-Mi LEE
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Publication number: 20080090356Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.Type: ApplicationFiled: December 13, 2007Publication date: April 17, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Chul PARK, Jun SEO, Tae-Hyuk AHN, Hyuk-Jin KWON, Jong-Heui SONG, Dae-Keun KANG
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Patent number: 7358126Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: GrantFiled: January 17, 2006Date of Patent: April 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Patent number: 7326619Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.Type: GrantFiled: July 28, 2004Date of Patent: February 5, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Chul Park, Jun Seo, Tae-Hyuk Ahn, Hyuk-Jin Kwon, Jong-Heui Song, Dae-Keun Kang
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Publication number: 20070194294Abstract: In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.Type: ApplicationFiled: February 21, 2007Publication date: August 23, 2007Inventors: Jong-Heui Song, Yong-Sun Ko, Jae-Seung Hwang, Jun Seo
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Publication number: 20070090435Abstract: A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.Type: ApplicationFiled: November 21, 2006Publication date: April 26, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Chul PARK, Jong-Heui SONG
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Publication number: 20070093021Abstract: A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.Type: ApplicationFiled: November 21, 2006Publication date: April 26, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Chul PARK, Jong-Heui SONG
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Patent number: 7157770Abstract: A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.Type: GrantFiled: July 1, 2004Date of Patent: January 2, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Chul Park, Jong-Heui Song
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Publication number: 20060163738Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: ApplicationFiled: January 17, 2006Publication date: July 27, 2006Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae