Abstract: A internal voltage generator includes a plurality of voltage level detection units, each configured to detect a voltage level of a corresponding internal voltage terminal, based on a predetermined target voltage level assigned to the corresponding internal voltage terminal, and generate a detection signal, a common internal voltage generation unit configured to generate an internal voltage through a pumping operation in response to the detection signal outputted from the voltage level detection units, and a path multiplexing unit configured to selectively output the internal voltage to one of the internal voltage terminals.

Abstract: A test circuit of a semiconductor apparatus includes a test temperature information generation section, an erroneous operation prevention unit, and a refresh cycle adjustment unit. The test temperature information generation section outputs test temperature information having a plurality of bits in a test operation mode, and irregularly changes logic values of the plurality of bits and transition time points of the logic values. The erroneous operation prevention unit generates a temperature compensation signal in response to the test temperature information. The refresh cycle adjustment unit changes a cycle of a reference refresh signal in response to the temperature compensation signal, and generates a refresh signal.

Abstract: Provided are a liquid crystal composition and a liquid crystal display (LCD) including the liquid crystal composition. The LCD includes a first display panel a second display panel facing the first display panel, and a liquid crystal composition disposed between the first display panel and the second display panel. If a dielectric constant in a direction parallel to a long axis of liquid crystals is defined as a horizontal dielectric constant ??, a dielectric constant in a direction perpendicular to the long axis of the liquid crystals is defined as a vertical dielectric constant ??, and the difference between the vertical dielectric constant ?? and the horizontal dielectric constant ?? is defined as dielectric anisotropy ??, then a ratio ??/?? of the dielectric anisotropy ?? to the vertical dielectric constant ?? of the liquid crystal composition is 0.5 or less.

Abstract: A semiconductor memory device includes an internal voltage generating circuit and a memory cell. The internal voltage generating circuit is configured to compare a temperature voltage, which has a level varying with a predetermined slope according to a level change of an internal voltage, with a variable reference voltage, which has a level varying according to a temperature change, and pump the internal voltage. The memory cell includes a cell transistor having a threshold voltage controlled according to the internal voltage.

Abstract: A reference voltage generation circuit configured to generate a reference voltage level that is compensated for based on an internal temperature change, where the reference voltage level is adjusted based on a resistance value controlled in response to a control signal.

Abstract: An internal voltage generation circuit includes a driving control signal generation unit configured to receive a temperature signal enabled when the internal temperature is below a preset temperature and generate first and second driving control signals, and an internal voltage generation unit configured to receive the first and second driving control signals and generate an internal voltage.

Abstract: A liquid crystal display (LCD) including a liquid crystal panel, and a gate driver which applies a gate signal having a driving frequency equal to or greater than 100 Hz to the liquid crystal panel. The liquid crystal panel comprises a first display panel, a second display panel facing the first display panel, and a liquid crystal composition disposed between the first display panel and the second display panel and includes liquid crystals.

Abstract: A method of fabricating liquid crystal display (LCD) that may improves picture quality by removing uncured monomers in a liquid crystal panel and an LCD obtained by the method are provided. The method includes forming a liquid crystal layer between a first substrate and a second substrate by injecting liquid crystal molecules and monomers between the first substrate and the second substrate, the first and second substrates facing each other; applying an electric field to the liquid crystal layer; performing a primary curing operation on the monomers; and removing the electric field and performing a secondary curing operation on remaining monomers, wherein at least one of the primary curing operation and the secondary curing operation includes maintaining a temperature of the liquid crystal layer below a phase transition temperature of the liquid crystal molecules.

Abstract: A method of manufacturing a liquid crystal display includes; forming a mother substrate assembly by disposing a liquid crystal mixture layer having liquid crystals and a light curable alignment supplement between a first mother substrate and a second mother substrate of a liquid crystal display, and disposing a light curable sealant surrounding the liquid crystal mixture layer, pre-tilting liquid crystal molecules of the liquid crystal mixture layer by applying a voltage to the first mother substrate and the second mother substrate, and simultaneously hardening the alignment supplement and the sealant by radiating light to the mother substrate assembly while applying the voltage to the first mother substrate and the second mother substrate.

Abstract: A semiconductor memory device includes an internal voltage generating circuit and a memory cell. The internal voltage generating circuit is configured to compare a temperature voltage, which has a level varying with a predetermined slope according to a level change of an internal voltage, with a variable reference voltage, which has a level varying according to a temperature change, and pump the internal voltage. The memory cell includes a cell transistor having a threshold voltage controlled according to the internal voltage.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and second drain electrodes; and first and second pixel electrodes electrically connected to the first and second electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.

Abstract: A method of manufacturing a liquid crystal display includes providing a first display panel, providing a second display panel, disposing liquid crystals and an alignment additive between the first display panel and the second display panel, applying a gradually increasing pre-tilting voltage to the first display panel and the second display panel, and hardening the alignment additive.

Abstract: A liquid crystal display (LCD) comprises a first substrate comprising a pixel electrode comprising one or more first domain-forming features and further comprising a first vertical alignment film disposed on the pixel electrode; a second substrate facing the first substrate and comprising a common electrode which comprises one or more second domain-forming features and further comprises a second vertical alignment film disposed on the common electrode; and a liquid crystal compound interposed between the first and second substrates, wherein the liquid crystal compound comprises liquid crystal molecules, ultraviolet (UV) hardening monomers and UV hardening initiators, and the liquid crystal molecules are pre-tilted to form an angle greater than 88 degrees but less than 90 degrees with respect to the first substrate when no driving power is applied to the pixel and common electrodes. Fast response time is provided in some embodiments.

Abstract: An internal voltage generation circuit includes a driving control signal generation unit configured to receive a temperature signal enabled when the internal temperature is below a preset temperature and generate first and second driving control signals, and an internal voltage generation unit configured to receive the first and second driving control signals and generate an internal voltage.

Abstract: In a vertical alignment liquid crystal display, a thin film transistor is formed on a first insulating substrate, and a pixel electrode (ITO) including cutouts (OPEN) is formed on the first substrate or a second substrate. A width of the cutouts of the upper and lower substrates gradually increases or decreases along a length thereof.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes a first field generating electrode with a plurality of cutouts. A thin film transistor is connected to the first field generating electrode. An auxiliary electrode is overlapped with one or more of the plurality of cutouts of the first field generating electrode, and is floated during the period of image display. A second field generating electrode faces the first field generating electrode and a liquid crystal layer is interposed between the first and second field generating electrodes. The liquid crystal layer includes a plurality of liquid crystal molecules and photo-polymers.

Abstract: An array substrate includes; a thin-film transistor layer including; a gate line, a data line disposed substantially perpendicular to the gate line, and a switching element connected to the gate line and the data line, a gate insulation layer disposed on the gate line, a passivation layer disposed on the thin-film transistor layer, a shielding electrode disposed on the passivation layer, an insulation layer disposed on the shielding electrode; and a pixel electrode including a micro-slit pattern, the pixel electrode being disposed on the insulation layer and electrically connected to the switching element, wherein the shielding electrode is vertically aligned with the data line and the shielding electrode blocks an electromagnetic fringe field of the data line from effecting the pixel electrode.

Abstract: An internal voltage generation circuit includes a temperature detection unit which detects an internal temperature of a semiconductor memory device and generates a temperature signal, a driving control signal generation unit which receives the temperature signal and generates first and second driving control signals, and an internal voltage generation unit which receives the first and second driving control signals and generates an internal voltage.

Abstract: A internal voltage generator includes a plurality of voltage level detection units, each configured to detect a voltage level of a corresponding internal voltage terminal, based on a predetermined target voltage level assigned to the corresponding internal voltage terminal, and generate a detection signal, a common internal voltage generation unit configured to generate an internal voltage through a pumping operation in response to the detection signal outputted from the voltage level detection units, and a path multiplexing unit configured to selectively output the internal voltage to one of the internal voltage terminals.

Abstract: A liquid crystal display includes: a substrate; a pixel electrode disposed on the substrate and having a first subpixel electrode and a second subpixel electrode; and a common electrode facing the pixel electrode, wherein the first subpixel electrode has a pair of bent edges substantially parallel to each other, the second subpixel electrode has a pair of bent edges substantially parallel to each other, and the second subpixel electrode has a height greater than a height of the first subpixel electrode.