Patents by Inventor Jong Ho You

Jong Ho You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10529859
    Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung Chan Ryu, Jong Ho You, Hyung Jong Lee
  • Patent number: 10361159
    Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Ho You, Sang Young Kim, Byung Chan Ryu
  • Publication number: 20190148538
    Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.
    Type: Application
    Filed: May 24, 2018
    Publication date: May 16, 2019
    Inventors: Byung Chan Ryu, Jong Ho You, Hyung Jong Lee
  • Patent number: 10141447
    Abstract: A semiconductor device includes an active fin extended in a first direction on a substrate. A gate structure extends in a second direction, wherein the gate structure intersects the active fin and covers an upper portion of the active fin. A source/drain region is positioned on the active fin adjacent to the gate structure. A silicide layer is on the source/drain region. A contact plug is connected to the source/drain region. A void is present between the silicide layer and the contact plug.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Ho You, Deok Han Bae, Sang Young Kim
  • Publication number: 20180286808
    Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.
    Type: Application
    Filed: November 22, 2017
    Publication date: October 4, 2018
    Inventors: Jong Ho You, Sang Young Kim, Byung Chan Ryu
  • Publication number: 20180286810
    Abstract: A semiconductor device includes an active fin extended in a first direction on a substrate. A gate structure extends in a second direction, wherein the gate structure intersects the active fin and covers an upper portion of the active fin. A source/drain region is positioned on the active fin adjacent to the gate structure. A silicide layer is on the source/drain region. A contact plug is connected to the source/drain region. Avoid is present between the silicide layer and the contact plug.
    Type: Application
    Filed: December 14, 2017
    Publication date: October 4, 2018
    Inventors: Jong Ho You, Deok Han Bae, Sang Young Kim