Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.

Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.

Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: Disclosed is a bit line selection circuit having hierarchical structure capable of preventing delay of operation speed due to signal loading by selecting a bit line with a sub bit line selection driver in a hierarchically shared bit line sense amp.

Abstract: Disclosed is a bit line selection circuit having hierarchical structure capable of preventing delay of operation speed due to signal loading by selecting a bit line with a sub bit line selection driver in a hierarchically shared bit line sense amp.

Abstract: Circuit for controlling a sense amplifier, is disclosed, which restores a signal delayed by line loading for faster operation of the sense amplifier in a case every one or every group of a few of the sense amplifiers is provided with one sense amplifier drive for faster data sensing of the sense amplifier, including signal transmission means for compensating a signal /SP or SN for controlling a drive of a sense amplifier for a path basis transmission delay in addition to a sense amplifier pull-up driver and a sense amplifier pull-down driver for driving sense amplifiers connected to one pair of bit lines B/L, and /BL for a positive, and a negative signals, and a sense amplifier driver precharge circuit for precharging the sense amplifier drivers when the sense amplifier are not in operation.