Patents by Inventor Jong-Hoon Na

Jong-Hoon Na has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9330913
    Abstract: A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Hyun You, Jong-Min Lee, Dong-Hwa Kwak, Tae-Yong Kim, Jong-Hoon Na, Young-Woo Park, Dong-Sik Lee, Jee-Hoon Han
  • Patent number: 8878332
    Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Na, Young-Woo Park, Dong-Hwa Kwak, Tae-Yong Kim, Jee-Hoon Han, Jang-Hyun You, Dong-Sik Lee, Su-Jin Park
  • Publication number: 20140231953
    Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 21, 2014
    Inventors: Jong-Hoon NA, Young-Woo PARK, Dong-Hwa KWAK, Tae-Yong KIM, Jee-Hoon HAN, Jang-Hyun YOU, Dong-Sik LEE, Su-Jin PARK
  • Patent number: 8748286
    Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Na, Young-Woo Park, Dong-Hwa Kwak, Tae-Yong Kim, Jee-Hoon Han, Jang-Hyun You, Dong-Sik Lee, Su-Jin Park
  • Publication number: 20120122297
    Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
    Type: Application
    Filed: August 4, 2011
    Publication date: May 17, 2012
    Inventors: Jong-Hoon NA, Young-Woo Park, Dong-Hwa Kwak, Tae-Yong Kim, Jee-Hoon Han, Jang-Hyun You, Dong-Sik Lee, Su-Jin Park
  • Publication number: 20110316165
    Abstract: A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.
    Type: Application
    Filed: October 27, 2010
    Publication date: December 29, 2011
    Inventors: JANG-HYUN YOU, JONG-MIN LEE, DONG-HWA KWAK, TAE-YONG KIM, JONG-HOON NA, YOUNG-WOO PARK, DONG-SIK LEE, JEE-HOON HAN
  • Publication number: 20090224330
    Abstract: A semiconductor memory device and method of manufacturing the same are disclosed. The semiconductor memory device includes a semiconductor substrate having a cell region and a peripheral circuit region, first transistors provided on the semiconductor substrate, a first semiconductor layer provided on the first transistors, and bonded by a bonding technique, and second transistors provided on the first semiconductor layer, wherein the first and second transistors are provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer, respectively, and a metal layer is formed on gates of the first and second transistors respectively provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer. As a result, the transistors in the peripheral circuit region requiring high performance can be formed on an upper layer and a lower layer.
    Type: Application
    Filed: May 19, 2009
    Publication date: September 10, 2009
    Inventors: Chang Min Hong, Han-Byung Park, Soon-Moon Jung, Hoon Lim, Kun-Ho Kwak, Byoung-Keun Son, Jong-Hoon Na, Yeon-Wook Jung, Ju-Young Lim