Abstract: An embodiment unitized fuel cell includes a cell frame including an electricity generating assembly (EGA) bonded to a frame, the cell frame including a manifold hole disposed at an end part of the frame and a reaction gas guide part extending from the manifold hole, wherein the manifold hole is configured to allow a reaction gas to pass therethrough, and a pair of bipolar plates respectively laminated on both sides of the cell frame, the pair of bipolar plates including a first bipolar plate configured to form a flow path of the reaction gas together with the reaction gas guide part of the cell frame, the first bipolar plate having a recessed hole disposed on a part corresponding to the reaction gas guide part to expose a part of the reaction gas guide part therethrough and a second bipolar plate bonded to the cell frame.

Abstract: In an embodiment, a unitized fuel cell includes a cell frame, a plurality of separators each including a cooling medium guide part extending from a manifold hole and having a selected area, a plurality of support protrusions protruding from the guide part of each of the separators toward the cooling surface, spaced apart from each other, and including a cooling medium flow field between the spaced protrusions, and an adhesive medium between the cell frame and the reaction surface on the guide part of each of the separators to provide a coupling force to each of the separators and the cell frame. In some embodiments, the adhesive medium does not overlap the plurality of support protrusions on the guide part.

Abstract: An embodiment integrated unit cell for a fuel cell stack includes an insert constructed with a membrane electrode assembly and a pair of gas diffusion layers disposed on opposite surfaces of the membrane electrode assembly, a frame having a form of a sheet, the frame being disposed to surround a periphery of the insert in an outer boundary region of the insert and joined to any one of opposite surfaces of the periphery of the insert by a first adhesive member at an interface thereof, and a pair of separators disposed on opposite surfaces of the frame, respectively, and joined to the opposite surfaces of the frame by second adhesive members.

Abstract: A storage device may read a plurality of data units from a host memory buffer prior to entering a low power mode, release a communication link with the host after reading the plurality of data unit, execute a background operation based on at least one of the plurality of data units, and enter into the low power mode after executing the background operation.

Abstract: An electronic device includes at least one processor, at least one antenna, and a wireless communication circuit electrically connected to the at least one processor and the at least one antenna. The wireless communication circuit includes a switch including a first terminal electrically connected to a path corresponding to a first frequency band, a second terminal electrically connected to a path corresponding to a second frequency band, and a third terminal selectively connected to a corresponding terminal of the first terminal and the second terminal and a filter circuit electrically connected between the third terminal and the at least one antenna and having a designated resonant frequency band. The wireless communication circuit selectively transmits a signal in one corresponding frequency band between the first frequency band and the second frequency band based on a terminal which is connected to the third terminal.

Abstract: An electronic device includes at least one processor, at least one antenna, and a wireless communication circuit electrically connected to the at least one processor and the at least one antenna. The wireless communication circuit includes a switch including a first terminal electrically connected to a path corresponding to a first frequency band, a second terminal electrically connected to a path corresponding to a second frequency band, and a third terminal selectively connected to a corresponding terminal of the first terminal and the second terminal and a filter circuit electrically connected between the third terminal and the at least one antenna and having a designated resonant frequency band. The wireless communication circuit selectively transmits a signal in one corresponding frequency band between the first frequency band and the second frequency band based on a terminal which is connected to the third terminal.

Abstract: According to one embodiment of the present invention, the scheduling method includes an acquisition step of acquiring operation state information on a virtual CPU (vCPU) and lock information on an OS in the operation of the vCPU and of a virtual machine (VM) driving the vCPU and including the OS, and a determination step for determining whether the vCPU is in a lock holder preemption (LHP) state on the basis of the operation state information and the lock information. According to one embodiment of the present invention, the LHP can be easily and precisely known on a system using the VM. Also, even with an increase in the number of cores, scalability can be supported in a system by adjusting the pCPU to which operations of the vCPU are allocated through a scheduling scheme.

Abstract: According to one embodiment of the present invention, the scheduling method includes an acquisition step of acquiring operation state information on a virtual CPU (vCPU) and lock information on an OS in the operation of the vCPU and of a virtual machine (VM) driving the vCPU and including the OS, and a determination step for determining whether the vCPU is in a lock holder preemption (LHP) state on the basis of the operation state information and the lock information. According to one embodiment of the present invention, the LHP can be easily and precisely known on a system using the VM. Also, even with an increase in the number of cores, scalability can be supported in a system by adjusting the pCPU to which operations of the vCPU are allocated through a scheduling scheme.

Abstract: An apparatus and method for in-loop filtering based on a largest coding unit (LCU) to reduce an external memory access bandwidth. An in-loop filter may include an external memory to store decoded frames, an internal memory to store pixels in use for deblocking filtering and sample adaptive offset filtering, a horizontal deblocking filter to perform deblocking filtering on input pixels in a horizontal direction with respect to vertical edge boundaries within an input area, a vertical deblocking filter to perform deblocking filtering in a vertical direction with respect to horizontal edge boundaries within the input area, and a sample adaptive offset filter to perform sample adaptive offset filtering.

Abstract: A sample adaptive offset (SAO) processing apparatus reusing an input buffer and an operation method of the SAO processing apparatus may include a SAO parameter parser to parse SAO parameter information from a bitstream; a SAO parameter adjuster to extract SAO type information and offset information from the parsed SAO parameter information; and a filtering performer to perform filtering on the bitstream based on the SAO type information and the offset information.