Patents by Inventor Jong Hye Cho

Jong Hye Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240103362
    Abstract: Disclosed herein is a method of printing a nanostructure including: preparing a template substrate on which a pattern is formed; forming a replica pattern having an inverse phase of the pattern by coating a polymer thin film on an upper portion of the template substrate, adhering a thermal release tape to an upper portion of the polymer thin film, and separating the polymer thin film from the template substrate; forming a nanostructure by depositing a functional material on the replica pattern; and printing the nanostructure deposited on the replica pattern to a substrate by positioning the nanostructure on the substrate, applying heat and pressure to the nanostructure, and weakening an adhesive force between the thermal release tape and the replica pattern by the heat.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 28, 2024
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jong Min KIM, Seung Yong LEE, So Hye CHO, Ho Seong JANG, Jae Won CHOI, Chang Kyu HWANG
  • Publication number: 20240091759
    Abstract: Disclosed herein is a method of depositing a transition metal single-atom catalyst including preparing a carbon carrier, and depositing a transition metal single-atom catalyst on the carbon carrier, in which the carbon carrier is surface-treated by an oxidation process, and wherein the deposition is carried out by an arc plasma process.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jong Min KIM, Sang Hoon KIM, Chang Kyu HWANG, Seung Yong LEE, So Hye CHO, Jae Won CHOI
  • Patent number: 8148267
    Abstract: A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Whee Won Cho, Jong Hye Cho
  • Patent number: 7611964
    Abstract: The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: November 3, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jong Hye Cho, Whee Won Cho, Eun Soo Kim
  • Publication number: 20090170321
    Abstract: A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.
    Type: Application
    Filed: June 11, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Whee Won Cho, Jong Hye Cho
  • Publication number: 20090170281
    Abstract: The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer.
    Type: Application
    Filed: June 27, 2008
    Publication date: July 2, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jong Hye CHO, Whee Won CHO, Eun Soo KIM
  • Publication number: 20090029522
    Abstract: A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material.
    Type: Application
    Filed: December 12, 2007
    Publication date: January 29, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Whee Won Cho, Seung Hee Hong, Suk Joong Kim, Jong Hye Cho
  • Publication number: 20090004818
    Abstract: Disclosed herein is a method of fabricating a semiconductor flash memory device, which method avoids and prevents damage to the conductive layer of a floating gate. The disclosed method can prevent a reduction in the charge trap density characteristics and improve the yield of the device.
    Type: Application
    Filed: December 14, 2007
    Publication date: January 1, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Seung Woo Shin, Eun Soo Kim, Suk Joong Kim, Jong Hye Cho
  • Publication number: 20080268612
    Abstract: The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer.
    Type: Application
    Filed: December 21, 2007
    Publication date: October 30, 2008
    Inventors: Whee Won Cho, Cheol Mo Jeong, Jung Geun Kim, Suk Joong Kim, Jong Hye Cho