Abstract: A deep source/drain region and a source/drain extension region may be formed in a semiconductor substrate adjacent to a gate electrode. A first silicide layer may be formed on the source/drain extension region. A gate spacer may be formed on a sidewall of the gate electrode to cover the first silicide layer. A second silicide layer may be formed on the deep source/drain region outside the gate spacer.

Abstract: An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.

Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.

Abstract: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.

Abstract: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.

Abstract: A metal interconnect layer of a semiconductor device, and a method for forming a metal interconnect layer of a semiconductor device are provided. The lower portion of a metal interconnect layer is wider than the upper portion of the metal interconnect layer. In another interconnect structure in accordance with the invention, the middle portion of the metal interconnect layer is wider than the upper and lower portions of the metal interconnect layer.

Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

Abstract: A metal interconnect layer of a semiconductor device, and a method for forming a metal interconnect layer of a semiconductor device are provided. The lower portion of a metal interconnect layer is wider than the upper portion of the metal interconnect layer. In another interconnect structure in accordance with the invention, the middle portion of the metal interconnect layer is wider than the upper and lower portions of the metal interconnect layer.

Abstract: In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

Abstract: In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

Abstract: Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, which can reproduce a profile of a gate electrode in a stable manner. The method includes forming an active pattern on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, forming a gate insulating layer on the channel regions, and forming a patterned gate electrode on the gate insulating layer while maintaining a shape conformal to the active pattern.

Abstract: A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating layer pattern; an epitaxial layer formed on the second region of the semiconductor substrate so as to have a predetermined thickness; spacers formed on sidewalls of the gate conductive layer pattern and part of the surface of the epitaxial layer; a lightly-doped first impurity region formed in the semiconductor substrate disposed below the spacers and in the epitaxial layer; and a heavily-doped second impurity region formed in a portion of the semiconductor substrate, exposed by the spacers.

Abstract: In an asymmetrical SRAM device, and a method of manufacturing the same, the asymmetrical SRAM device includes a semiconductor substrate on which a plurality of unit cell regions are defined, and a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate, wherein the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions.

Abstract: A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating layer pattern; an epitaxial layer formed on the second region of the semiconductor substrate so as to have a predetermined thickness; spacers formed on sidewalls of the gate conductive layer pattern and part of the surface of the epitaxial layer; a lightly-doped first impurity region formed in the semiconductor substrate disposed below the spacers and in the epitaxial layer; and a heavily-doped second impurity region formed in a portion of the semiconductor substrate, exposed by the spacers.

Abstract: In a method of forming a gate of a semiconductor device, a gate insulating layer and a polysilicon layer are successively formed on a substrate that is partitioned into a field region and an active region. A hard mask is formed on the polysilicon layer. The hard mask overlaps with the active region and has a spacer pattern that partially extends into the field region. The polysilicon layer is partially etched using the hard mask as an etching mask to form the gate. The gate overlaps with the active region and has an end portion positioned in the field region. The end portion has a width at least as large as a thickness of the spacer pattern.

Abstract: In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

Abstract: In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.

Abstract: In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

Abstract: An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.

Abstract: A flip chip type semiconductor device comprises at least one first metal line and at least a pair of second metal lines formed in the passivation layer, an aluminum pad covering the first metal line, an aluminum fuse covering the pair of second metal lines adjacent to each other and the passivation layer therebetween, and an under-bump metal layer pattern and a bump formed on the aluminum pad in order. The first and second metal lines are formed respectively in first and second grooves by using a damascene process after forming first and second grooves in the passivation layer.