Abstract: The present disclosure relates to a technology of preparing an anion exchange composite membrane including: a porous polymer support; and a polyfluorene-based anion exchange membrane or a polyfluorene-based anion exchange membrane having a cross-linked structure formed on the support, and applying the same to alkaline fuel cells, water electrolysis, carbon dioxide reduction, metal-air batteries, etc. The polyfluorene-based anion exchange composite membrane including a porous polymer support according to the present disclosure has remarkably improved mechanical properties, dimensional stability, durability, long-term stability, etc.

Abstract: A multi-chip package includes a plurality of semiconductor devices each having an address which is designated based on unique values corresponding to the respective semiconductor devices; and a controller suitable for activating each of the semiconductor devices based on the address, and controlling the activated semiconductor device to perform a normal operation.

Abstract: A multi-chip package includes a plurality of semiconductor devices each having an address which is designated based on unique values corresponding to the respective semiconductor devices; and a controller suitable for activating each of the semiconductor devices based on the address, and controlling the activated semiconductor device to perform a normal operation.

Abstract: A method of 4-bit MLC programming a nonvolatile memory device includes inputting an mth program operation command and sequentially executing first to fourth logical page program operations according to first to fourth logical page program start voltages, each stored in first to fourth logical page program start voltage storage units, wherein a program voltage, which is applied at a time point at which a memory cell programmed higher than a lowest verify voltage while a program operation of each logical page is performed occurs for a first time, is updated to each logical page program start voltage.

Abstract: An integrated circuit includes a first internal voltage generation unit configured to generate a first voltage and output the first voltage through an internal voltage terminal in an active operation period, a second internal voltage generation unit configured to generate a second voltage and output the second voltage through the internal voltage terminal in an initial section of a standby operation period, and a third internal voltage generation unit configured to generate a third voltage and output the third voltage through the internal voltage terminal in the remaining section of the standby operation period.

Abstract: A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal.

Abstract: Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks.

Abstract: A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal.

Abstract: A flash memory device includes a plurality of memory blocks and a plurality of block selection circuits corresponding to the plurality of memory blocks. All of the block selection circuits are sequentially operated in response to block control signals, or two or more of the block selection circuits are operated in response to the block control signals.

Abstract: Multi-level cell programming methods are provided. A method includes providing a page buffer including first and second registers connected to first and second memory cell blocks, respectively. A least significant bit (LSB) program of each memory cell is completed. Most significant bit (MSB) data is set in a first node of the first register. An MSB program is performed. When the MSB program is performed at a first verify voltage, first data at a first voltage level is set in the first node. When the MSB program is performed at a second verify voltage, second data at a second voltage level, opposite to the first voltage level, is set in the first node. When the MSB program is performed at a third verify voltage, the first data is set in the first node. The MSB program is repeated according to the first node data.

Abstract: A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing reference data set for the verifying operation in a second latching circuit; programming the data stored in the first latching circuit to the multi level cell; and verifying the programming of the data through a first node or a second node in the second latching circuit in accordance with a verifying voltage.

Abstract: A method of 4-bit MLC programming a nonvolatile memory device includes inputting an mth program operation command and sequentially executing first to fourth logical page program operations according to first to fourth logical page program start voltages, each stored in first to fourth logical page program start voltage storage units, wherein a program voltage, which is applied at a time point at which a memory cell programmed higher than a lowest verify voltage while a program operation of each logical page is performed occurs for a first time, is updated to each logical page program start voltage.

Abstract: According to an aspect of a method of programming a nonvolatile memory device, a first program operation command is input, and a program operation is executed according to a program start voltage stored in a program start voltage storage unit. Here, a program voltage, which is applied at a time point at which a memory cell programmed higher than a verify voltage while the program operation is performed occurs for the first time, is updated to a program start voltage.

Abstract: A non-volatile memory device comprises a voltage supplier comprising memory cells in which the voltage supplier supplies a positive set voltage to a bulk of a memory cell array at the time of a read operation of the memory cells and a controller for controlling the voltage supplier to set and supply a bulk voltage depending on a number of erase/program cycles of the memory cell array.

Abstract: A method of programming nonvolatile memory devices. A program operation is performed by applying a dummy program pulse having a pulse width wider than a pulse width of a program start pulse. A program operation is performed by applying the program start pulse. It is then verified whether a program has been completed as a result of the program operation. A program operation is performed by applying a step-shaped dummy program pulse, which has a second pulse width and has been increased by a second step voltage. A program operation is performed by applying a program pulse having a first step voltage and a first pulse width. It is then verified whether a program has been completed as a result of the program operation.

Abstract: Multi-level cell programming methods are provided. A method includes providing a page buffer including first and second registers connected to first and second memory cell blocks, respectively. A least significant bit (LSB) program of each memory cell is completed. Most significant bit (MSB) data is set in a first node of the first register. An MSB program is performed. When the MSB program is performed at a first verify voltage, first data at a first voltage level is set in the first node. When the MSB program is performed at a second verify voltage, second data at a second voltage level, opposite to the first voltage level, is set in the first node. When the MSB program is performed at a third verify voltage, the first data is set in the first node. The MSB program is repeated according to the first node data.

Abstract: A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array.

Abstract: A page buffer includes a first register, a second register and a data I/O unit. The first register temporarily stores data to be programmed into cells included in a first memory cell block group, or reads and stores data of a corresponding memory cell. The second register temporarily stores data to be programmed into cells included in a second memory cell block group, or reads and stores data of a corresponding memory cell. The data I/O unit inputs specific data to the first register and the second register, or outputs data stored in the first register and the second register.

Abstract: A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing reference data set for the verifying operation in a second latching circuit; programming the data stored in the first latching circuit to the multi level cell; and verifying the programming of the data through a first node or a second node in the second latching circuit in accordance with a verifying voltage.

Abstract: A semiconductor memory device having a number of chips, each of the chips including a chip enable detection unit configured to simultaneously output a first signal and a second signal in response to a chip enable signal, a chip operation detection unit configured to output an operation state signal in response to the first signal, and an internal circuit configured to operate in response to a power source voltage and a control signal in response to the second signal being received.