Patents by Inventor Jong Il Won
Jong Il Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12646964Abstract: There is provided a battery system including: a main switch configured to supply or cut off a voltage of a battery to a load; a semiconductor pre-charger module which includes a semiconductor switch configured to supply or cut off the voltage of the battery to the load, and a semiconductor switch driver configured to output a pulse signal for driving the semiconductor switch to turn on and off the semiconductor switch, and is connected in parallel with the main switch; and a controller configured to generate a control signal for controlling the main switch and the semiconductor pre-charger module, wherein the semiconductor switch driver of the semiconductor pre-charger module includes an isolation element configured to electrically isolate the controller and the voltage of the battery. Here, the semiconductor switch of the semiconductor pre-charger module may be a metal-oxide-semiconductor (MOS)-controlled thyristor (MCT).Type: GrantFiled: January 11, 2023Date of Patent: June 2, 2026Assignee: Electronics and Telecommunications Research InstituteInventors: Dong Yun Jung, Kun Sik Park, Jong Il Won, Hyun-Gyu Jang, Doohyung Cho, Jong-Won Lim
-
Patent number: 11784247Abstract: A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions areType: GrantFiled: June 10, 2021Date of Patent: October 10, 2023Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kun Sik Park, Jong Il Won, Doo Hyung Cho, Dong Yun Jung, Hyun Gyu Jang
-
Publication number: 20230231404Abstract: There is provided a battery system including: a controller; a main switch controlled by the controller to supply or cut off a voltage of a battery to a load; and a semiconductor pre-charger module including a semiconductor switch connected in parallel with the main switch and configured to supply or cut off the voltage of the battery to the load according to a control signal output from the controller, and a semiconductor switch driver configured to receive the control signal from the controller and output a single pulse signal for driving the semiconductor switch to turn on and off the semiconductor switch. Here, the semiconductor switch driver of the semiconductor pre-charger module includes an isolation element configured to electrically isolate the controller and the battery voltage, and the semiconductor switch of the semiconductor pre-charger module is a MOS-controlled thyristor (MCT).Type: ApplicationFiled: January 11, 2023Publication date: July 20, 2023Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Dong Yun JUNG, Kun Sik PARK, JONG IL WON, Hyun-Gyu JANG, Doohyung CHO, Jong-Won LIM
-
Patent number: 11637192Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.Type: GrantFiled: June 23, 2021Date of Patent: April 25, 2023Assignee: Electronics and Telecommunications Research InstituteInventors: Kun Sik Park, Jong Il Won, Doo Hyung Cho, Hyun Gyu Jang, Dong Yun Jung
-
Publication number: 20220299554Abstract: The apparatus for ESD test includes a micro-controller unit client, a low voltage supply configured to output a low voltage on the basis of control by the micro-controller unit, a high voltage supply configured to output a high voltage on the basis of control by the micro-controller unit, and an ESD generator configured to generate an ESD voltage for an ESD test of a device under test (DUT) by using the low voltage and the high voltage, on the basis of control by the micro-controller unit. The ESD generator is a semiconductor integrated circuit module where a charging semiconductor switch, a discharging semiconductor switch, a switch driving block controlling a switching operation of each of the charging semiconductor switch and the discharging semiconductor switch, and a plurality of passive elements connected to the charging semiconductor switch and the discharging semiconductor switch are implemented as package, for generating the ESD voltage.Type: ApplicationFiled: October 26, 2021Publication date: September 22, 2022Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Dong Yun JUNG, Hyun Gyu JANG, Kun Sik PARK, JONG IL WON, Sung Kyu KWON, Jong Won LIM, Doo Hyung CHO
-
Publication number: 20220020671Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.Type: ApplicationFiled: July 20, 2021Publication date: January 20, 2022Applicant: Electronics and Telecommunications Research InstituteInventors: Dong Yun JUNG, Hyun Gyu JANG, Sung Kyu KWON, Kun Sik PARK, Jong Il WON, Seong Hyun LEE, Jong Won LIM, Doo Hyung CHO
-
Publication number: 20210408265Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.Type: ApplicationFiled: June 23, 2021Publication date: December 30, 2021Applicant: Electronics and Telecommunications Research InstituteInventors: Kun Sik PARK, Jong Il WON, Doo Hyung CHO, Hyun Gyu JANG, Dong Yun JUNG
-
Patent number: 11115393Abstract: One or more example embodiments include user terminals, methods, and/or computer-readable recording mediums storing computer programs, in which information encrypted or decrypted not to be decoded by a message server that controls transmission and reception of messages between one or more user terminals is not shared with the message server. One or more example embodiments include user terminals, methods, and/or computer-readable recording mediums storing computer programs, which encrypt a first message by using an encryption key, transmit the first message from a first user terminal to a second user terminal, and decrypt a second message received from the second user terminal by using the encryption key.Type: GrantFiled: February 7, 2019Date of Patent: September 7, 2021Assignee: LINE CorporationInventors: Ki Bin Shin, Jong Il Won
-
Patent number: 11063919Abstract: One or more example embodiments include user terminals, methods, and/or computer-readable recording mediums storing computer programs, in which information encrypted or decrypted not to be decoded by a message server that controls transmission and reception of messages between one or more user terminals is not shared with the message server. One or more example embodiments include user terminals, methods, and/or computer-readable recording mediums storing computer programs, which encrypt a first message by using an encryption key, transmit the first message from a first user terminal to a second user terminal, and decrypt a second message received from the second user terminal by using the encryption key.Type: GrantFiled: February 7, 2019Date of Patent: July 13, 2021Assignee: LINE CorporationInventors: Ki Bin Shin, Jong Il Won
-
Patent number: 10230697Abstract: A non-transitory computer-readable recording medium storing computer-readable instructions that, when executed by a first user terminal, cause the first user terminal to perform a method including: receiving a first message including a first attached file, generating at least one encryption key for encrypting the first message by taking into account a type of the first attached file, encrypting the first attached file of the first message by using the encryption key, adding sender information of the first message to the first message, and transmitting the first message including the sender information to a message server, may be provided.Type: GrantFiled: July 6, 2016Date of Patent: March 12, 2019Assignee: Line CorporationInventors: Ki Bin Shin, Jong Il Won
-
Patent number: 9123548Abstract: Provided is a semiconductor device. The semiconductor device includes: a first semiconductor layer having a first region with a first device and a second region with a second device; a device isolation pattern provided in the first semiconductor layer and electrically separating the first device and the second device from each other; a drain provided on a lower surface of the first region of the first semiconductor layer; and a second semiconductor layer provided on a lower surface of the second region of the first semiconductor layer.Type: GrantFiled: July 31, 2014Date of Patent: September 1, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jin-Gun Koo, Jong Il Won, Hyun-cheol Bae, Sang Gi Kim, Yil Suk Yang