Abstract: A pulse width modulation (PWM) data recovery device includes a differential-to-single (DTS) circuit configured to generate a PWM bit using a differential data signal including a differential positive data signal and a differential negative data signal, and an alignment buffer configured to activate a bit lock signal by detecting a synch pattern, recover symbol data by receiving the PWM bit in synchronization with one of the differential positive data signal and the differential negative data signal, and transmit the symbol data in synchronization with a reference clock.

Abstract: A pulse width modulation (PWM) data recovery device includes a differential-to-single (DTS) circuit configured to generate a PWM bit using a differential data signal including a differential positive data signal and a differential negative data signal, and an alignment buffer configured to activate a bit lock signal by detecting a synch pattern, recover symbol data by receiving the PWM bit in synchronization with one of the differential positive data signal and the differential negative data signal, and transmit the symbol data in synchronization with a reference clock.

Abstract: An output buffer circuit in a multi-power system operating at a high power supply voltage and a low power supply voltage includes a pre-driver, and a main driver. The pre-driver performs a differential switching operation on first and second differential input signals to output first and second differential output signals. The main driver performs a differential switching operation on the DC-eliminated and level-shifted first and second differential output signals to output third and fourth differential output signals. The main driver includes a differential switching circuit including first and second NMOS transistors, and performs a differential switching operation on the DC-eliminated and level-shifted first and second differential output signals to output the third and fourth differential output signals, and an equalizer coupled between source electrodes of the first and second NMOS transistors, and controls a bandwidth of the third and fourth differential output signals.

Abstract: A variable voltage gain amplifier in an automatic voltage gain control circuit includes a denominator current source that generates a denominator current corresponding to a denominator a numerator current source that generates a numerator current corresponding to a numerator, and a differential amplifier that amplifies an input voltage with a variable voltage gain and generates an output voltage that is substantially dB-linear with the input voltage when the variable voltage gain that is expressed as an exponential function of a control voltage is approximated to a fraction where each of a denominator and a numerator is expressed as a third order polynomial function of the control voltage.