Abstract: A memory system includes: a storage device for storing data; a system memory in which normal firmware and debugging firmware are stored; a firmware implementer for implementing the normal firmware or the debugging firmware; and a controller for controlling the storage device in a normal mode in which the memory system is driven by the normal firmware. When an error detected in the normal mode is uncorrectable, the controller uploads the debugging firmware stored in the system memory to the firmware implementer to change the normal mode to a debugging mode. The firmware implementer performs a debugging operation on the storage device by implementing the uploaded debugging firmware.

Abstract: An ion beam etching apparatus comprising a plasma chamber, a plasma source disposed on top of the plasma chamber and configured to generate plasma, a process chamber defining a treating area where a substrate is treated, a grid structure disposed between the process chamber and the plasma chamber, wherein the grid structure receives the plasma, and supplies ions or radicals toward the substrate, a discharge line connected to the grid structure, and a first pumping system connected to the discharge line, wherein particles or polymers within the grid structure are discharged through the discharge line.

Abstract: The present disclosure relates to a memory controller which supports an interworking method for a test between an external device and a storage device, and a host. The memory controller proposed in the present disclosure may include a first interface configured to communicate with an external device, a second interface configured to communicate with a memory, a command queue configured to store commands received from the external device and a processor configured to perform a control operation according to a command stored in the command queue, and suspend the performance of the control operation according to the command for a waiting time corresponding to a value of a mutex counter for the command, when a mutex flag for the command is activated.

Abstract: Provided herein are a memory controller and a method of operating the same. The memory controller may include a background condition storage and a background controller. The background condition storage may be configured to store a trigger condition for each background operation for a memory device in each of a non-charging mode and a charging mode associated with a battery for the memory controller. The background controller may be configured to change the trigger condition from a non-charging condition to a charging condition depending on charging information indicating whether the battery for the memory controller is in a charging state. The trigger condition is mitigated in the charging condition compared to the non-charging condition.

Abstract: An apparatus for manufacturing a display device includes a chamber, a heating member disposed inside the chamber to provide a thermal atmosphere inside the chamber, where the heating member includes a first heater and a second heater facing each other, a height adjustment member including an end disposed between the first heater and the second heater, and a driving unit which drives the end of the height adjustment member to move up or down such that the end of the height adjustment member is located at one of a first height and a second height which are different heights between the first heater and the second heater. Each of the first height and the second height is different from a height of a top surface of the first heater, and different from a height of a bottom surface of the second heater facing the top surface of the first heater.

Abstract: Provided is an operation method of a memory controller which includes obtaining first read data from a second external device based on a first read command received from a first external device and performing error correction and decoding on the first read data to determine whether reading is successful or unsuccessful, performing a hard decoding-based read recovery operation and a soft decoding-based read recovery operation when a read failure occurs as a result of the first read operation, determining whether there is a second read command queued when the hard decoding-based read recovery has failed, temporarily stopping the read recovery operation for the first read data when there is the second read command queued and obtaining second read data by reading data from the second external device based on the second read command and performing error correction and decoding on the second read data.

Abstract: An autonomous vehicle is provided which includes: at least one sensor configured to detect surrounding environment of the vehicle and to generate surrounding environment information; a processor, during autonomous driving of the vehicle, configured to generate vehicle state information by monitoring a state of the vehicle, and to determine whether a minimum risk maneuver (MRM) is required based on at least one of the surrounding environment information and the vehicle state information; and a controller configured to control operations of the vehicle under the control of the processor, wherein, based on a determination that the MRM is required, the processor is configured to determine an MRM type, and when the determined MRM type is a shoulder stop, the processor is configured to generate at least one stop position candidate group.

Abstract: Provided herein may be an electronic device and a method of operating the same. The electronic device may include a memory device including a replay protected memory block (RPMB) configured to store security data, a memory controller configured to control the memory device, and a host device configured to verify, using a password, an external device coupled thereto wherein the memory controller controls the memory device to read, when the external device is verified, the security data, and wherein the host device is further configured to encrypt the read security data, and transmit, to the verified external device, the encrypted security data, a decryption key for decrypting the encrypted security data, and an RPMB key for accessing the security data.

Abstract: A memory system includes: a plurality of memory dies each including a plurality of memory blocks each including a plurality of pages, each of the memory dies being configured to store therein map data having a tree structure and a memory controller configured to organize super blocks each including memory blocks from the respective memory dies, configured to control an operation of copying data from a first memory block to a second memory block among the plurality of memory blocks and configured to update the map data according to the operation.

Abstract: A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.

Abstract: The present disclosure relates to a display device and a driving method thereof, wherein a refresh rate of pixels is controlled at a reference frame frequency in a normal driving mode, and the refresh rate of the pixels is controlled at a frequency lower than the reference frame frequency in a low speed driving mode. In the low speed driving mode, park data is transmitted to a data driving circuit during at least one vertical blank period.

Abstract: A memory system includes a non-volatile memory device and a controller. The non-volatile memory device includes a first memory region and a second memory region. The controller stores, into the second memory region, copied data of original data stored in the first memory region and an address of the first memory region while storing, into the first memory region, an address of the second memory region, when detecting occurrence of a critical event.

Abstract: A dry etching method includes a first step of adsorbing first radicals into a surface of an etching target, wherein the first radicals are contained in first plasma generated from a plasma generator; and a second step of irradiating ion-beams extracted from second plasma generated from the plasma generator onto the surface of the etching target into which the radicals have been adsorbed, thereby desorbing a surface atomic layer of the etching target, wherein the first step is performed such that: a positive potential greater than a potential of the first plasma is applied to one or two selected from first to third grids, while a ground potential is applied to the rest thereof; and a negative potential equal to or lower than a potential of the third grid is applied to a substrate support structure.

Abstract: An apparatus for controlling autonomous driving of a vehicle is introduced. The apparatus may comprise at least one sensor to capture surrounding environment data, a processor, and a controller configured to control operations of the vehicle. During autonomous driving, the processor may generate vehicle state information and determine whether a minimal risk maneuver is to be performed, potentially mitigating collision risks. Upon determining to perform the minimal risk maneuver, the processor may determine a maneuver type and a target location. The processor may control, based on the determined maneuver type and the target location, autonomous driving of the vehicle by causing the controller to operate the vehicle to stop at the target location.

Abstract: Various embodiments relate to a vehicle for performing minimum risk maneuvers and a method of operating the same. An autonomous driving vehicle includes at least one sensor configured to detect surrounding environment of the vehicle to generate surrounding environmental information, a controller configured to control an operation of the vehicle, and a processor. The processor is configured to monitor the status of the vehicle to generate vehicle state information; determine whether a minimal risk maneuver is required; execute, based on the minimal risk maneuver being required, the minimal risk maneuver by causing the controller to control autonomous driving of the vehicle; provide, to a user inside the vehicle, an indication of initiation of the minimal risk maneuver; and turn on and off an external indicator indicating the execution of the minimal risk maneuver.

Abstract: Memory systems and operating methods of the memory systems are disclosed. In an implementation, a memory system includes a system buffer including buffer areas to which addresses are allocated, and configured to store data in the buffer areas, and a buffer manager configured to designate an address of a buffer area in which a defect occurs as a defect address by comparing a first parity bit for data stored in the system buffer with a second parity bit that is obtained by a computation based on the data stored in the system buffer, and block access to the buffer area designated as the defect address.

Abstract: A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.

Abstract: A memory system may include: a memory device including a plurality of memory cells, and a controller including: an internal reception queue suitable for queueing a command queued in an external transmission queue, the command being externally provided to the controller, and an internal transmission queue suitable for queueing a response to the command, the response being transmitted from the controller and to be queued in an external reception queue, wherein the controller is suitable for controlling the memory device on the basis of the command to generate the response.

Abstract: Provided is an operation method of a memory controller which includes obtaining first read data from a second external device based on a first read command received from a first external device and performing error correction and decoding on the first read data to determine whether reading is successful or unsuccessful, performing a hard decoding-based read recovery operation and a soft decoding-based read recovery operation when a read failure occurs as a result of the first read operation, determining whether there is a second read command queued when the hard decoding-based read recovery has failed, temporarily stopping the read recovery operation for the first read data when there is the second read command queued and obtaining second read data by reading data from the second external device based on the second read command and performing error correction and decoding on the second read data.

Abstract: A computing system includes host and a storge device. The host includes a host memory and a user interface. The storage device provides the host with a first request including device setting inquiry information, and sets a device configuration based on a first response to the device setting inquiry information received from the host. The host provides the storage device with the first response acquired from a user through the user interface in response to the first request. The device setting inquiry information includes at least one of information on allocation of a map buffer in the host memory, information on allocation of a write buffer in a buffer region of the storage device, or information on a power level of the storage device.