Abstract: In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device.

Abstract: In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device.

Abstract: In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

Abstract: A lateral double-diffused MOS (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate 202 formed of a material having p-conductivity type impurities, a drift region formed of a material having n-conductivity type impurities on the semiconductor substrate, a first buried layer 206 of p-type material and a second buried layer 208 formed of n-type material. Layers 206 and 208 are arranged at the boundary between the semiconductor substrate and the drift region. A first well region 210 of p-type material contacts the first buried layer 206 n-type in a first portion 1 of the drift region.

Abstract: A lateral double-diffused MOS (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate 202 formed of a material having p-conductivity type impurities, a drift region formed of a material having n-conductivity type impurities on the semiconductor substrate, a first buried layer 206 of p-type material and a second buried layer 208 formed of n-type material. Layers 206 and 208 are arranged at the boundary between the semiconductor substrate and the drift region. A first well region 210 of p-type material contacts the first buried layer 206 n-type in a first portion 1 of the drift region.

Abstract: In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

Abstract: A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and has corner portions at one side thereof. The high breakdown voltage isolation region has an isolation region for electrically separating the low and high voltage regions from each other and a lateral double diffused metal-oxide-semiconductor (DMOS) transistor for transmitting a signal from the low voltage region to the high voltage region. In particular, a drain region of the lateral DMOS transistor is disposed between the corner portions of the high voltage region, and opposite edges of the corner portions of the high voltage region and drain region of the lateral DMOS transistor are curved.

Abstract: A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and has corner portions at one side thereof The high breakdown voltage isolation region has an isolation region for electrically separating the low and high voltage regions from each other and a lateral double diffused metal-oxide-semiconductor (DMOS) transistor for transmitting a signal from the low voltage region to the high voltage region. In particular, a drain region of the lateral DMOS transistor is disposed between the corner portions of the high voltage region, and opposite edges of the corner portions of the high voltage region and drain region of the lateral DMOS transistor are curved.

Abstract: A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed.

Abstract: A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed.