Abstract: In a semiconductor device and method of manufacturing thereof, a first insulation interlayer is formed on a substrate including a lower conductive pattern. The first insulation interlayer has a first opening through which the lower conductive pattern is exposed. An interconnection is formed in the first opening such that the interconnection is contact with the lower conductive pattern and protruded from the first insulation interlayer. A second insulation interlayer is formed on the first insulation interlayer in such a manner that the second insulation interlayer has a second opening through the interconnection is exposed and the second opening is centrally aligned with the interconnection. An upper conductive pattern is formed in the second opening such that the upper conductive pattern is contacted with the interconnection. Accordingly, a mis-alignment between the upper conductive pattern and the interconnection is prevented.

Abstract: An interconnection structure for a semiconductor device, and a method of forming the same, having a tolerance to high temperature and high speed while not suffering from a problem of a drawing out of a first lower metal pattern. In addition, a second lower metal pattern may be formed, not using a patterning process including a photolithography process, but using a selection etching characteristic instead. Therefore, the second lower metal pattern is self-aligned to the first lower metal pattern, thereby making up for a decrease of a margin in the photolithography process with increasing high integration. As a result, the present invention may be employed to fabricate a semiconductor device to be more highly integrated.