Abstract: A semiconductor apparatus may include an interface circuit. The interface circuit may sense level variations of a first signal and a second signal. The interface circuit may generate first and second output signals by variably delaying the first and second signals depending on a sensing result. The interface circuit may transmit the first and second output signals to first and second signal transmission lines which are adjacent to each other.

Abstract: A transmitting device may include a logic circuit, a transmission controller, and a transmission driver. The encoder may generate transmission control signals based on control symbols. The transmission controller may generate driving control signals based on the transmission control signals. The transmission driver may drive a wire to one level among multiple levels, based on the driving control signals.

Abstract: A buffer circuit may include an amplification circuit, a main load circuit, and a sub-load circuit. The amplification circuit and the main load circuit may generate first and second output signals by amplifying first and second input signals. The sub-load circuit may compensate mismatch between rising timing and falling timing of the first output signal based on the first input signal.

Abstract: A buffer circuit may include an amplification circuit, a main load circuit, and a sub-load circuit. The amplification circuit and the main load circuit may generate first and second output signals by amplifying first and second input signals. The sub-load circuit may compensate mismatch between rising timing and falling timing of the first output signal based on the first input signal.

Abstract: A semiconductor apparatus may include an interface circuit. The interface circuit may sense level variations of a first signal and a second signal. The interface circuit may generate first and second output signals by variably delaying the first and second signals depending on a sensing result. The interface circuit may transmit the first and second output signals to first and second signal transmission lines which are adjacent to each other.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a training entry signal and a transmission signal. The second semiconductor device may generate selection codes and a control signal in response to the training entry signal. The second semiconductor device may adjust a level of a reference voltage signal for buffering the transmission signal in response to the selection codes and control a capacitance of an internal node. The reference voltage signal may be outputted from the internal node in response to the control signal.

Abstract: A transmitting device may include an encoder, a timing transmission controller, and a transmission driver. The encoder may generate transmission control signals according to control symbols. The timing transmission controller may generate driving control signals from the transmission control signals. The transmission driver may drive each of wires to one level among multiple levels, based on the driving control signals. The timing transmission controller may control generation timings of the driving control signals according to levels to which the wires are to be driven.

Abstract: A transmitting device may include an encoder, a timing transmission controller, and a transmission driver. The encoder may generate transmission control signals according to control symbols. The timing transmission controller may generate driving control signals from the transmission control signals. The transmission driver may drive each of wires to one level among multiple levels, based on the driving control signals. The timing transmission controller may control generation timings of the driving control signals according to levels to which the wires are to be driven.

Abstract: A transmitting device may include a logic circuit, a transmission controller, and a transmission driver. The encoder may generate transmission control signals based on control symbols. The transmission controller may generate driving control signals based on the transmission control signals. The transmission driver may drive a wire to one level among multiple levels, based on the driving control signals.

Abstract: A semiconductor device may include a comparator and a pad. The comparator may compare a voltage level of a reference node with a voltage level of a reference voltage to generate a code. The comparator may include an output driver modeling unit configured to adjust a current flowing to the reference node depending on a code value of the code to the reference node. The pad may be coupled to the reference node. A total impedance of the reference node, the output driver modeling unit, and components and signal lines coupled therebetween may correspond to a total impedance of the reference node, the pad, and components and signal lines coupled therebetween.

Abstract: A system may include an interface circuit coupled to a wire bus. The interface circuit may receive a multi-level symbol according to a status of the wire bus. The interface circuit may include a clock recovery circuit configured to generate a recovered clock based on the multi-level symbol. The interface circuit may latch the multi-level symbol based on one of an external clock and the recovered clock according to an operation speed of the system.

Abstract: A system may include an interface circuit coupled to a wire bus. The interface circuit may receive a multi-level symbol according to a status of the wire bus. The interface circuit may include a clock recovery circuit configured to generate a recovered clock based on the multi-level symbol. The interface circuit may latch the multi-level symbol based on one of an external clock and the recovered clock according to an operation speed of the system.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a training entry signal and a transmission signal. The second semiconductor device may generate selection codes and a control signal in response to the training entry signal. The second semiconductor device may adjust a level of a reference voltage signal for buffering the transmission signal in response to the selection codes and control a capacitance of an internal node. The reference voltage signal may be outputted from the internal node in response to the control signal.

Abstract: A semiconductor device include: a first reception inductor pad through configured to receive data from a first transmission inductor pad; a second reception inductor pad configured to receive a clock from a second transmission inductor pad; and a data recovery unit configured to generate an output data.

Abstract: A semiconductor device include: a first reception inductor pad through configured to receive data from a first transmission inductor pad; a second reception inductor pad configured to receive a clock from a second transmission inductor pad; and a data recovery unit configured to generate an output data.