Patents by Inventor Jong Ju

Jong Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070015314
    Abstract: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.
    Type: Application
    Filed: September 11, 2006
    Publication date: January 18, 2007
    Applicant: ChipPAC, Inc
    Inventors: Sang Ho Lee, Jong Ju, Hyeog Kwon
  • Publication number: 20050269676
    Abstract: Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device such as a die, or a package, or a heat spreader, in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package (an “upper” package) is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate (that is, the upper package may be inverted), or so that the die attach side of the upper package faces away from the lower die or lower package substrate.
    Type: Application
    Filed: May 20, 2005
    Publication date: December 8, 2005
    Applicant: ChipPAC, Inc
    Inventors: Sang Lee, Jong Ju, Hyeog Kwon, Marcos Karnezos
  • Publication number: 20050258527
    Abstract: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.
    Type: Application
    Filed: October 20, 2004
    Publication date: November 24, 2005
    Applicant: ChipPAC, Inc.
    Inventors: Sang Lee, Jong Ju, Hyeog Kwon
  • Publication number: 20050208701
    Abstract: Individual pieces of film adhesive (42) are placed on a support surface (46). Diced semiconductor chips (24) are individually placed on the individual pieces of the film adhesive thereby securing the diced semiconductor chips to the support surface to create first chip subassemblies (52). The diced semiconductor chip and support surface of each of a plurality of the first chip subassemblies are electrically connected, such as by wires (54), to create second chip subassemblies ((56). At least a portion of at least some of the second chip subassemblies are encapsulated, such as with molding compound (58), to create semiconductor chip packages (60).
    Type: Application
    Filed: October 29, 2004
    Publication date: September 22, 2005
    Applicant: ChipPAC, Inc.
    Inventors: Jin-Wook Jeong, In-Sang Yoon, Hee Lee, Hyun-Joon Oh, Hyeog Kwon, Jong Ju, Sang Lee
  • Publication number: 20050208700
    Abstract: A semiconductor chip packaging method (34) includes printing an adhesive (46) on a support surface (42), typically a surface of a semiconductor substrate (44), to create individual adhesive areas (40). Semiconductor chips (24) are individually placed on the individual adhesive areas thereby securing the semiconductor chips to the support surface to create first chip subassemblies (55). The semiconductor chip and the semiconductor substrate are electrically connected to create second chip subassemblies (62). At least a portion of each of at least some of the second chip subassemblies is encapsulated to create semiconductor chip packages (64). The adhesive at the individual adhesive areas is preferably a B-staged adhesive so that solvent is removed from the adhesive before the individually placing step.
    Type: Application
    Filed: October 15, 2004
    Publication date: September 22, 2005
    Applicant: ChipPAC, Inc.
    Inventors: Hyeog Kwon, Sang Lee, Jong Ju