Abstract: Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. Each die of the first subset of dies is configured to be selectively enabled to receive commands in response to a first chip enable signal, and each die of a second subset of dies of the plurality of dies is configured to be selectively enabled to receive commands in response to a second chip enable signal independent of the first chip enable signal, wherein the first subset of dies and the second subset of dies are mutually exclusive.

Abstract: Provided herein are methods that relate to a novel therapeutic strategy for treatment of heart and/or cardiovascular diseases. The method includes administration of LOXL2 inhibitors for treating, preventing, or ameliorating at least one symptom associated with heart and/or cardiovascular diseases.

Abstract: Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. Each die of the first subset of dies is configured to be selectively enabled to receive commands in response to a first chip enable signal, and each die of a second subset of dies of the plurality of dies is configured to be selectively enabled to receive commands in response to a second chip enable signal independent of the first chip enable signal, wherein the first subset of dies and the second subset of dies are mutually exclusive.

Abstract: Apparatus facilitating peak power management are useful in mitigating excessive current levels within a multi-die package. For example, such apparatus may include an array of memory cells, a controller for performing an access operation on the array of memory cells, an input buffer having an input connected to a clock signal line and having an output, a clock generator for generating an internal clock signal, an output buffer having an input connected to receive the internal clock signal and having an output connected to the clock signal line, and a counter for counting pulses of a particular clock signal selected from a group consisting of the internal clock signal from the clock generator and an external clock signal from the output of the input buffer.

Abstract: Apparatus facilitating peak power management are useful in mitigating excessive current levels within a multi-die package. For example, such apparatus may include an array of memory cells, a controller for performing an access operation on the array of memory cells, an input buffer having an input connected to a clock signal line and having an output, a clock generator for generating an internal clock signal, an output buffer having an input connected to receive the internal clock signal and having an output connected to the clock signal line, and a counter for counting pulses of a particular clock signal selected from a group consisting of the internal clock signal from the clock generator and an external clock signal from the output of the input buffer.

Abstract: Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include generating a clock signal in a particular die of a plurality of dies, counting pulses of the clock signal in a wrap-around counter in each die of the plurality of dies, and pausing an access operation for the particular die of the plurality of dies at a designated point until a value of the wrap-around counter matches an assigned counter value of the particular die.

Abstract: Provided herein are methods that relate to a novel therapeutic strategy for treatment of heart and/or cardiovascular diseases. The method includes administration of LOXL2 inhibitors for treating, preventing, or ameliorating at least one symptom associated with heart and/or cardiovascular diseases.

Abstract: Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include generating a clock signal in a particular die of a plurality of dies, counting pulses of the clock signal in a wrap-around counter in each die of the plurality of dies, and pausing an access operation for the particular die of the plurality of dies at a designated point until a value of the wrap-around counter matches an assigned counter value of the particular die.

Abstract: Disclosed are a side emitting lens, a light emitting device using the side emitting lens, a mold assembly for preparing the side emitting lens and a method for preparing the side emitting using the mold assembly. The lens of the present invention has a simple structure so the lens is easily fabricated through a molding process. If the lens is applied to the light emitting member, light generated from the light emitting member is laterally guided by means of the lens.

Abstract: An apparatus for monitoring an operator vibration for an earth moving machinery with an operation cab is disclosed.

Abstract: Disclosed is an LED device, a method for manufacturing the same, and a light emitting apparatus having the same. The LED device includes (a) a light emitting diode unit and (b) an adjustment layer laminated on a light emitting surface of the light emitting diode unit, a fine pattern having being formed on the adjustment layer by repeating a shape in a light emission direction. The adjustment layer is (i) at least one layer formed by aligning transparency adjustment particles having a shape or (ii) a polymer film layer having a fine pattern imprinted on the polymer film layer so as to adjust transparency. A fine pattern adjustment layer having various shapes and an adjustable size is introduced on the light emitting surface of the LED unit. As a result, the light extraction efficiency of the surface of the LED unit improves together with ease of manufacturing and secured uniformity.

Abstract: A method for fabricating an LED having section grown on a sapphire substrate, a boded structure, and a unit chip separated from the bonded structure. The method includes (a) bonding the section grown on a first surface of the sapphire substrate to a first surface of a first substrate with a first binder; (b) bonding a second surface of the first substrate to a first surface of a second substrate with a second binder; (c) removing the second substrate from a bonded structure obtained as a result of step (b) after polishing a second surface of the sapphire substrate; (d) separating the bonded structure into unit chips after the second substrate has been removed; and (e) bonding the second surface of the polished sapphire substrate provided in each unit chip to a lead frame, and removing the first substrate. This method improves heat dissipation efficiency.

Abstract: A light emitting diode devic that includes (a) a light emitting diode section, (b) an electrically conductive pad section being disposed outside the light emitting diode section and being electrically connected to an external power source, and (c) at least one electrically conductive interconnection section for connecting the electrically conductive pad section to one side or both sides of the light emitting diode section. In the light emitting diode device, a wire is connected to the electrically conductive pad section disposed outside the light emitting diode section, and the electrically conductive pad section is connected to one side of the light emitting diode section by means of at least one electrically conductive interconnection section, so that not only it is easy to uniformly coat a fluorescent substance, but also an area covering vertically emitted light can be reduced to enhance a light extraction efficiency of the light emitting diode device.

Abstract: The present invention relates to a memory application tester for testing a semiconductor memory device comprising a plurality of motherboards having a memory socket. The motherboards are vertically mounted and effectively integrated so that a memory application tester may test more memory device simultaneously, and a limit in the trace length due to the integration of the motherboards is effectively solved.

Abstract: The present invention relates to a method of controlling LNA in a mobile communication terminal that may improve receiving rate of mobile communication terminal in an area with multiple pseudo noise (PN). Preferably, the method may comprise the acts of: measuring Ec/Io of pilot signal received through receiving stage of the mobile communication terminal; determining whether the measured Ec/Io is higher than a predetermined standard Ec/Io or not; notifying an LNA controlling unit controlling the LNA that the measured Ec/Io is lower than the standard Ec/Io, in a case where the Ec/Io is lower than the standard Ec/Io as a result of the determination; and controlling the LNA to be operated in high gain mode according to the notification that the Ec/Io is lower than the standard Ec/Io.

Abstract: A simplified manufacturing process for massive production of LEDs that have superior light emitting efficiency and superior heat discharging efficiency. The method employs a laser lift-off technique instead of the flip-chip bonding technique and it does not require a photolithography process, thereby substantially reducing the process steps and enhancing the heat discharging efficiency. The LED chips are formed as unit chips before irradiating the laser, thereby increasing the yield and realizing the mass production by preventing cleavage of the crystal structures. Heat discharging efficiency is also increased by roughening the surface of an n-type GaN layer. The light emitting area can be widened 30% more than in the flip-chip technique. Thus, the present invention serves to increase the light output and the heat discharging area, thereby drastically enhancing the performance of manufacturing high-output LEDs.

Abstract: Disclosed is a light emitting diode (LED) device that comprises a crystal structure of a sapphire substrate-free gallium nitride (GaN) LED, wherein the crystal structure is mounted on a first surface of a sub-mount substrate in the form of a unit chip, and the first surface of the sub-mount substrate has a surface area greater than the surface area of a region in which the unit chip is bonded. Preforms for manufacturing the LED device and a method for manufacturing the LED device are also disclosed. The sapphire substrate, on which the crystal structure of the light emitting diode has grown, is processed into a unit chip before being removed. Thus, any crack in the crystal structure of the light emitting diode that may occur during the removal of the sapphire substrate can be prevented. Therefore, a thin light emitting diode device can be manufactured in a mass production system.

Abstract: A glass handling tool and a method of moving a glass substrate are provided. The glass handling tool includes support members, moving members, and a body. The support members support a glass substrate. The moving members fix the support members. The body is coupled with the moving members.

Abstract: Disclosed is an algorithm pattern generator for testing a memory device. It has a configuration which can optimize a configuration of a memory tester including an address scrambling and a data scrambling in the memory tester for carrying out a test at a memory device module level or a component level.

Abstract: Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation boards, a DUT board, a backplane board, and a power supply unit. The pattern generation boards receive a test program, generate a test pattern signal and an expected signal, transmit the test pattern signal to the semiconductor devices, receive a test pattern result signal, compare the test pattern result signal with the expected signal, generate a Direct Current (DC) test signal and a DC test expected signal, transmit the DC test signal to the semiconductor devices, receive a DC test result signal and compare the DC test result signal with the DC test expected signal. The DUT board includes a plurality of sockets for connection to the semiconductor devices and a plurality of connectors for connection to the pattern generation boards.