Patents by Inventor Jong-Kook Kim
Jong-Kook Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970547Abstract: The present disclosure relates to a novel anti-HER2 antibody or an antigen-binding fragment thereof used in the prevention or treatment of cancer, a chimeric antigen receptor including the same, and uses thereof. The antibody of the present disclosure is an antibody that specifically binds to HER2 which is highly expressed in cancer cells (particularly, breast cancer or gastric cancer cells), and binds to an epitope that is different from an epitope to which trastuzumab binds.Type: GrantFiled: April 10, 2023Date of Patent: April 30, 2024Assignee: GC Cell CorporationInventors: Jong Seo Lee, Kyu Tae Kim, Young Ha Lee, In Sik Hwang, Bong Kook Ko, Eunji Choi, You-Sun Kim, Jeongmin Kim, Miyoung Jung, Hoyong Lim, Sungyoo Cho
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Publication number: 20240130109Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.Type: ApplicationFiled: December 15, 2023Publication date: April 18, 2024Inventors: Beom Ho MUN, Eun Jeong KIM, Jong Kook PARK, Seung Mi LEE, Ji Won CHOI, Kyoung Tak KIM, Yun Hyuck JI
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Patent number: 11950501Abstract: An organic light emitting device including: a substrate; a first electrode; a second electrode; and an organic layer interposed between the first electrode and the second electrode and including an emission layer, wherein one of the first electrode and the second electrode is a reflective electrode and the other is a semitransparent or transparent electrode, and wherein the organic layer includes a layer having at least one of the compounds having at least one carbazole group, and a flat panel display device including the organic light emitting device. The organic light emitting device has low driving voltage, excellent current density, high brightness, excellent color purity, high efficiency, and long lifetime.Type: GrantFiled: October 18, 2022Date of Patent: April 2, 2024Assignee: Samsung Display Co., Ltd.Inventors: Seok-Hwan Hwang, Young-Kook Kim, Yoon-Hyun Kwak, Jong-Hyuk Lee, Kwan-Hee Lee, Min-Seung Chun
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Patent number: 11936075Abstract: Disclosed are a separator for fuel cells capable of minimizing the volume of a system and the use of sealants, and a stack for fuel cells, more particularly, a stack for solid oxide fuel cells, including the same. Specifically, by adding a metal sheet having a specific shape, position and size to the separator, the stress applied to the sealant can be uniformized, and thus the oxidizing agent and fuel can be separated and electrically isolated using only a piece of sealant. Therefore, the stack for fuel cells is characterized in that there is no variation in temperature, reactant concentration, power, or the like between respective unit cells, so delamination and microcracks do not occur, the volume is minimized, and the power density per unit volume is very high.Type: GrantFiled: December 21, 2021Date of Patent: March 19, 2024Assignee: Korea Institute of Science and TechnologyInventors: Jong Ho Lee, Kyung Joong Yoon, Ji Won Son, Seong Kook Oh, Sang Hyeok Lee, Dong Hwan Kim, Min Jun Oh
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Publication number: 20230357598Abstract: Provided is a manufacturing method of a stainless steel sheet having etching patterns. The method includes: coating a coating composition on a stainless steel sheet to form a coating layer; and forming a matte coated film layer, having an etching effect, on the coating layer. The coating composition comprises: 10 to 30 wt% of a silane-based compound, 0.5 to 6 wt% of an organic acid, 0.1 to 3 wt% of a vanadium compound, 0.1 to 3 wt% of a magnesium compound, and a remainder of a solvent.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Inventors: Jin-Tae KIM, Ha-Na CHOI, Yang-Ho CHOI, Jung-Hwan LEE, Yon-Kyun SONG, Jong-Kook KIM
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Patent number: 11063346Abstract: Disclosed is a shark fin antenna for a vehicle. The shark fin antenna has a pad and a base disposed on the pad to provide a space for a printed circuit board and a plurality of antenna components. The shark fin antenna includes a holder having a groove therein for exposing at least a portion of an upper surface of a printed circuit board, a first antenna unit supported by the holder and having an antenna pattern formed on a surface thereof to receive an AM/FM frequency band signal, a first auxiliary unit covering at least a portion of an upper surface of the first antenna unit, and a spring mounted in the groove to elastically support the first auxiliary unit and the first antenna unit in a vertical direction of the upper surface of the printed circuit board.Type: GrantFiled: March 2, 2020Date of Patent: July 13, 2021Assignee: INFAC ELECS CO., LTD.Inventors: Tae Hoon Yang, Sang Hoon Lim, Soo Young Hwang, Ki Seok Uhm, Kyu Chang Nam, Chae Kyun Lim, Jong Kook Kim
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Publication number: 20210057805Abstract: Disclosed is a shark fin antenna for a vehicle. The shark fin antenna has a pad and a base disposed on the pad to provide a space for a printed circuit board and a plurality of antenna components. The shark fin antenna includes a holder having a groove therein for exposing at least a portion of an upper surface of a printed circuit board, a first antenna unit supported by the holder and having an antenna pattern formed on a surface thereof to receive an AM/FM frequency band signal, a first auxiliary unit covering at least a portion of an upper surface of the first antenna unit, and a spring mounted in the groove to elastically support the first auxiliary unit and the first antenna unit in a vertical direction of the upper surface of the printed circuit board.Type: ApplicationFiled: March 2, 2020Publication date: February 25, 2021Inventors: Tae Hoon Yang, Sang Hoon Lim, Soo Young Hwang, Ki Seok Uhm, Kyu Chang Nam, Chae Kyun Lim, Jong Kook Kim
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Publication number: 20200255687Abstract: Provided is a coating composition having excellent corrosion resistance and fingerprint resistance, and also provides a stainless steel sheet having etching patterns and a manufacturing method therefor, the stainless steel sheet comprising: a stainless steel sheet; a coating layer, which is formed on the stainless steel sheet and is a cured product of the coating composition; and a quenching coated film layer formed on the coating layer and having a quenching effect, wherein: the coating layer, formed by curing the coating composition having excellent corrosion resistance and fingerprint resistance, is transparent and has high gloss, thereby having an effect of enabling the surface characteristics of the stainless steel sheet to be expressed as they are; the stainless steel sheet having etching patterns has excellent corrosion resistance and fingerprint resistance even on the parts thereof on which the etching patterns are not formed.Type: ApplicationFiled: November 24, 2016Publication date: August 13, 2020Inventors: Jin-Tae KIM, Ha-Na CHOI, Yang-Ho CHOI, Jung-Hwan LEE, Yon-Kyun SONG, Jong-Kook KIM
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Patent number: 10391518Abstract: A method of manufacturing a transparent pattern printed steel plate includes forming a printed paint film layer by jetting transparent ink onto at least one surface of a steel plate, and curing the printed paint film layer with ultraviolet light to form a cured printed paint film layer. Further, a method of manufacturing a transparent pattern printed steel plate includes preparing a steel plate having a color painted film layer formed on at least one surface thereof, forming a printed paint film layer by jetting transparent ink onto the color painted film layer, and curing the printed paint film layer to form a cured printed paint film layer.Type: GrantFiled: August 19, 2015Date of Patent: August 27, 2019Assignee: POSCOInventors: Jin-Tae Kim, Jong-Sang Kim, Bong-Woo Ha, Yang-Ho Choi, Jung-Hwan Lee, Ha-Na Choi, Jong-Kook Kim
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Patent number: 10056321Abstract: A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate.Type: GrantFiled: October 31, 2013Date of Patent: August 21, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heung-Kyu Kwon, Jong-Kook Kim
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Publication number: 20170354991Abstract: A method of manufacturing a transparent pattern printed steel plate includes forming a printed paint film layer by jetting transparent ink onto at least one surface of a steel plate, and curing the printed paint film layer with ultraviolet light to form a cured printed paint film layer. Further, a method of manufacturing a transparent pattern printed steel plate includes preparing a steel plate having a color painted film layer formed on at least one surface thereof, forming a printed paint film layer by jetting transparent ink onto the color painted film layer, and curing the printed paint film layer to form a cured printed paint film layer.Type: ApplicationFiled: August 19, 2015Publication date: December 14, 2017Inventors: Jin-Tae KIM, Jong-Sang KIM, Bong-Woo HA, Yang-Ho CHOI, Jung-Hwan LEE, Ha-Na CHOI, Jong-Kook KIM
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Publication number: 20170012025Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.Type: ApplicationFiled: September 23, 2016Publication date: January 12, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Heung-Kyu KWON, Jong-Kook KIM, Ji-Chul KIM, Byeong-Yeon CHO
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Patent number: 9349713Abstract: Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package.Type: GrantFiled: March 25, 2015Date of Patent: May 24, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Kook Kim, Byoung-Wook Jang
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Publication number: 20160027764Abstract: Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package.Type: ApplicationFiled: March 25, 2015Publication date: January 28, 2016Inventors: Jong-Kook KIM, Byoung-Wook JANG
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Patent number: 9129826Abstract: In a semiconductor assembly having stacked elements, discrete bumps made of a polymer such as an electrically nonconductive epoxy are interposed between the upper surface of a substrate and the lower surface of the overhanging part of an elevated element (die or package) with the discrete bump directly under bond sites on the elevated element.Type: GrantFiled: May 30, 2006Date of Patent: September 8, 2015Assignee: STATS ChipPAC Ltd.Inventors: Hun Teak Lee, Jong Kook Kim, Chul Sik Kim, Ki Youn Jang
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Publication number: 20150051728Abstract: Provided is a detecting method of abnormality of a machine tool operation, and the detecting method includes a preparing step S100; a reference waveform obtaining step S200 of measuring a drive voltage and a drive current, while machining the material in a normal state of the machine tool, and obtaining a reference waveform; a monitoring section setting step S300 of setting a monitoring section and thus automatically calculating a maximum load value and a minimum load value; a permissible limit setting step S400 of setting maximum and minimum permissible limits; and a monitoring step S500 of obtaining a machining load generated and determining whether a difference between maximum and minimum load values of the machining load is out of the maximum or minimum permissive limit and then outputting normality or abnormality thereof.Type: ApplicationFiled: December 12, 2013Publication date: February 19, 2015Applicants: KOREA TOOL MONITORING CO., LTD., DASAN TOOL CO., LTD.Inventors: Byung-Hak KIM, Jong-Kook KIM
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Publication number: 20140312489Abstract: A flip-chip semiconductor package is provided that includes a semiconductor chip, a package substrate having a chip attachment surface on which bond sites are formed, and bumps attached to an active surface of the semiconductor chip and bonded to the bond sites, wherein the bond sites are radially arranged around a middle portion of the package substrate.Type: ApplicationFiled: January 15, 2014Publication date: October 23, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: HO-HYEUK IM, JONG-KOOK KIM, SU-MIN PARK
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Publication number: 20140159237Abstract: A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate.Type: ApplicationFiled: October 31, 2013Publication date: June 12, 2014Inventors: Heung-Kyu KWON, Jong-Kook KIM
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Publication number: 20130256916Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.Type: ApplicationFiled: February 1, 2013Publication date: October 3, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heung-Kyu KWON, Jong-Kook KIM, Ji-Chul KIM, Byeong-Yeon CHO
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Patent number: 8519517Abstract: A semiconductor package system, and method of manufacturing thereof, includes: an electrical substrate having a contact pad; a support structure having a lead finger thereon; a bump on the lead finger, the bump clamped on a top and a side of the lead finger and connected with the contact pad; and an encapsulant over the lead finger and the electrical substrate.Type: GrantFiled: July 29, 2011Date of Patent: August 27, 2013Assignee: Stats Chippac Ltd.Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang