Abstract: Disclosed is an electric power steering apparatus. The electric power steering apparatus includes: a torque sensor configured to detect a torque applied to a steering wheel; a current detector configured to measure a current flowing through a driving motor; and an electronic control unit configured to estimate a current flowing through the driving motor depending on the detected torque and compare the estimated current with the measured current to judge a malfunction of the torque sensor or the current detector.

Abstract: A diffusing film may have a microlens pattern and an embossed pattern on the surface thereof. The diffusing film includes a light entrance plane for receiving incident light, a light exit plane opposite the light entrance plane, the light exit plane for transmitting light, a plurality of microlenses on a surface of the light exit plane of the diffusing film, microlenses of the plurality of microlenses being spaced apart from one another, and a separation plane between the plurality of microlenses, the separation plane having an embossed pattern on a surface thereof.

Abstract: A method of extrusion molding a prism film and a prism film manufactured by the same, the method including providing a molten film, simultaneously forming a prism pattern and an embossed pattern on opposite surfaces of the molten film by passing the molten film through a gap between a prism roll and an emboss roll, and cooling the molten film having the prism pattern and the embossed pattern on opposite surfaces thereof.

Abstract: A method of extrusion molding a prism film and a prism film manufactured by the same, the method including providing a molten film, simultaneously forming a prism pattern and an embossed pattern on opposite surfaces of the molten film by passing the molten film through a gap between a prism roll and an emboss roll, and cooling the molten film having the prism pattern and the embossed pattern on opposite surfaces thereof.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: Method for fabricating a semiconductor device, including the steps of (1) forming a gate insulating film, a silicon layer, and an insulating film on a substrate in succession, (2) selectively removing a portion of the insulating film on which a gate electrode is to be formed, (3) forming first sidewalls at sides of the insulating film having the portion removed therefrom, (4) forming silicide on a surface of the exposed silicon, (5) forming a cap insulating film on the silicide and the first sidewalls, (6) removing the insulating film, and (7) using the cap insulating film as a mask in removing the exposed silicon layer, to form the gate electrode.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: A method of forming a twin well includes the steps of: forming a field oxide layer on a semiconductor substrate to define active regions of a device, and forming a first mask which exposes a predetermined active region of the semiconductor substrate; ion-implanting a first conductivity type impurity into the exposed region of the semiconductor substrate using the first mask as an ion implantation mask, to form a first well; ion-implanting a second conductivity type impurity to penetrate the first mask, to form a buried region which is self-aligned with the first well and comes into contact with the bottom of the field oxide layer; removing the first mask, and forming a second mask which is to expose the first well of the semiconductor substrate; and ion-implanting a second conductivity impurity into the exposed region of the semiconductor substrate to levels deeper and shallower than the buried region using the second mask as an ion implantation mask, to form a second well including the buried region.

Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.

Abstract: A method of forming an isolation region of a semiconductor device, includes the steps of forming a first insulating film on a substrate; defining a plurality of isolation regions on the first insulating film; removing portions of the first insulating film in the isolation regions to expose portions of the substrate; selectively removing the exposed portions of the substrate to form at least one trench; forming a second insulating film in the at least one trench and on portions of the first insulating film; and removing the first insulating film so as to remove the second insulating film formed thereon.

Abstract: A spinner which distributes a photoresist on a wafer in a semiconductor device fabrication apparatus includes a rotation-plate vacuum chuck which holds a wafer, a driving motor which rotates the chuck and a temperature controller assembly. The temperature controller assembly maintains a temperature distribution along the chuck within a predetermined temperature-distribution range. The temperature controller assembly includes a non-contact thermometer, a non-contact variable heater, and a heat regulator. By controlling the temperature in the chuck, a photoresist layer can be coated on a wafer with more uniform thickness than if the temperature were not controlled.

Abstract: A wafer spin coating system, for coating a layer of photoresist on a wafer, includes a spin coating unit, a pumping unit and a sensing unit. A first controller in the spin coating unit controls the operation of a rotating device with the wafer mounted thereon. The first controller also outputs a photoresist pumping operation order. A second controller in the pumping unit receives the pumping operation order and outputs a pumping operation commencing signal and a valve operation signal that opens and closes a valve to control a gas feeding operation. The sensing unit receives the pumping operation commencing signal and the valve operation signal, and selectively outputs an abnormal status control signal to the first controller to stop the pumping operations if an abnormality is detected.

Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.

Abstract: A structure and fabricating method of a thin film transistor which is suitable for an SRAM memory cell. The thin film transistor structure includes: an insulation substrate; a gate electrode formed on the insulation substrate; a gate insulation film formed on the gate electrode and on the insulation substrate; a semiconductor layer formed on the gate insulation film; channel regions formed in parts of the semiconductor layer at both sides of the gate electrode; a high density first conductive type first impurity region formed in the semiconductor layer over the gate electrode; and first conductive type second impurity regions of having an LDD structure formed in parts of the semiconductor layer over the insulation substrate except under the gate electrode.

Abstract: An improved twin well formation method for a semiconductor device capable of improving the latch-up characteristic in DRAM device which requires a high integration density and of improving a recess problem which occurs due to the capacitor, which includes the steps of a first step which forms an insulation film on a semiconductor substrate having a first region and a second region; a second step which forms a first temporary film on an insulation film of the first region; a third step which forms a first side wall spacer at the first temporary side wall; a fourth step which implants a first conductive ion to a substrate of a second region; a fifth step which forms a second temporary film on a substrate of the second region; a sixth step which removes the first temporary film; a seventh step which implants a second conductive ion to a substrate of the first region; and an eighth step which anneals and removes the second temporary film and the first insulation spacer.

Abstract: An electron gun for a color cathode ray tube includes a last accelerating electrode having a large-caliber electron beam passing hole for commonly passing red, blue, and green electron beams. Both ends of the beam passing hole include circular arc portions formed with a predetermined curvature. The center portions where the green electron beam passes through protrude by a predetermined width. The length of the protrusion in the horizontal direction satisfies the following inequality: L<H-2R(1+cos .alpha.), where H designates the horizontal width of the large-caliber electron beam passing hole, R is the radius of the circular arc portions and .alpha. is the angle between a line drawn from either center of the circular arc portions to an adjacent apex of the protrusions and a line connecting centers of both circular arc portions.