Abstract: A light emitting module including a circuit board and a lighting emitting device thereon and including first, second, and third LED stacks each including first and second conductivity type semiconductor layers, a first bonding layer between the second and third LED stacks, a second bonding layer between the first and second LED stacks, a first planarization layer between the second bonding layer and the third LED stack, a second planarization layer on the first LED stack, a lower conductive material extending along sides of the first planarization layer, the second LED stack, the first bonding layer, and electrically connected to the first conductivity type semiconductor layers of each LED stack, respectively, and an upper conductive material between the circuit board and the lower conductive material.

Abstract: An electrode assembly includes a first electrode; a second electrode; and a separator, the first electrode, the second electrode, and the separator wound about an axis defining a core and an outer circumference of the electrode assembly. The first electrode has a pair of first sides and a pair of second sides, a first portion extending between the pair of first sides, and a second portion extending between the pair of first sides, the first portion being coated with an active material, and at least a part of the second portion includes an electrode tab. The second portion includes a first part adjacent to the core of the electrode assembly, a second part adjacent to the outer circumference of the electrode assembly, and a third part between the first part and the second part. The first or second part has a smaller height than the third part.

Abstract: A system and method for managing medical information with enhanced personal information protection are disclosed. The system and method may generate a distributed key including a user key, an agent key, and a backup key, and manage medical data of a user, using a user agent assigned to each user and the distributed key, to prevent personal information of the user from being directly accessed from outside.

Abstract: A light emitting module including a circuit board and a lighting emitting device thereon and including first, second, and third LED stacks each including first and second conductivity type semiconductor layers, a first bonding layer between the second and third LED stacks, a second bonding layer between the first and second LED stacks, a first planarization layer between the second bonding layer and the third LED stack, a second planarization layer on the first LED stack, a lower conductive material extending along sides of the first planarization layer, the second LED stack, the first bonding layer, and electrically connected to the first conductivity type semiconductor layers of each LED stack, respectively, and an upper conductive material between the circuit board and the lower conductive material.

Abstract: A method for transmitting specific data whose data format is unknown at a relay from a first blockchain network to a second blockchain network via the relay is provided. The method includes steps of: the relay (a) in response to detecting that a blockchain communication message for transmitting the specific data from the first blockchain network following a first data format to the second blockchain network following a second data format is generated, generating a relay message including the blockchain communication message and verification information; and (b) transmitting the relay message to the second blockchain network, thereby instructing the second blockchain network to (i) verify the relay message by using the verification information included in the relay message and (ii) convert the specific data included in the relay message into the second data format to generate converted specific data and then transmit the converted specific data to a receiving party.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Abstract: An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Abstract: An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.

Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

Abstract: A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.

Abstract: An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.

Abstract: An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.