Patents by Inventor Jong Lam Lee
Jong Lam Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080001166Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.Type: ApplicationFiled: September 5, 2007Publication date: January 3, 2008Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Yoo
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Publication number: 20070295986Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.Type: ApplicationFiled: August 30, 2007Publication date: December 27, 2007Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Yoo
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Patent number: 7250638Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.Type: GrantFiled: September 23, 2005Date of Patent: July 31, 2007Assignee: LG Electronics Inc.Inventors: Jong-Lam Lee, In-kwon Jeong, Myung Cheol Yoo
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Patent number: 7214325Abstract: Forming low contract resistance metal contacts on GaN films by treating a GaN surface using a chlorine gas Inductively Coupled Plasma (ICP) etch process before the metal contacts are formed. Beneficially, the GaN is n-type and doped with Si, while the metal contacts include alternating layers of Ti and Al. Additionally, the GaN film is dipped in a solution of HCl:H2O prior to metal contact formation.Type: GrantFiled: March 22, 2002Date of Patent: May 8, 2007Assignee: LG Electronics Inc.Inventors: Jong Lam Lee, Ho Won Jang, Jong Kyu Kim, Changmin Jeon
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Publication number: 20060244001Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.Type: ApplicationFiled: January 7, 2005Publication date: November 2, 2006Applicant: LG Electronic Inc.Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Yoo
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Patent number: 7081401Abstract: A p-type ohmic electrode in a gallium nitride based(GaN based) optical device and a fabrication method thereof. The p-type ohmic electrode in a GaN based optical device is fabricated using a rutile structure transition metal layer, such as an Ru, Ir or Os layer, or an oxide layer thereof, or using a double layer comprised of an Ru layer as a base layer and an Ni layer, an ITO layer or an AuO layer on the Ru layer. Thus, the p-type ohmic electrode is good in light transmittance and is thermally stable while having low contact resistance with the p-GaN layer.Type: GrantFiled: March 19, 2003Date of Patent: July 25, 2006Assignee: Pohang University of Science and Technology FoundationInventors: Jong Lam Lee, Ho Won Jang
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Publication number: 20060099730Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.Type: ApplicationFiled: September 23, 2005Publication date: May 11, 2006Applicant: LG Electronics Inc.Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Yoo
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Publication number: 20060071230Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.Type: ApplicationFiled: September 23, 2005Publication date: April 6, 2006Applicant: LG Electronics Inc.Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Yoo
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Publication number: 20050098792Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.Type: ApplicationFiled: December 3, 2004Publication date: May 12, 2005Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Yoo
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Patent number: 6818467Abstract: A gallium nitride (GaN) based optical device and a fabrication method thereof are provided. The GaN based optical device includes a substrate, a p-type GaN (p-GaN) layer formed on the substrate, and a p-type ohmic electrode formed on the p-GaN layer, wherein the p-type ohmic electrode is formed of a triple layer comprised of a nickel (Ni) layer, a gold (Au) layer and an indium tin oxide (ITO) layer sequentially formed. The thicknesses of the Ni layer and the Au layer forming the triple layer are smaller than the thickness of the ITO layer. When the p-type ohmic electrode in the GaN based optical device is formed of a triple layer comprised of Ni/Au/ITO, the Ni/Au layers reduce contact resistance and the ITO, which is a transparent, conductive oxide layer, increases transparency and increases luminescence efficiency.Type: GrantFiled: March 24, 2003Date of Patent: November 16, 2004Assignee: Pohang University of Science and Technology FoundationInventors: Jong Lam Lee, Soo Young Kim, Ho Won Jang
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Patent number: 6762083Abstract: A method for manufacturing a hetero-junction field effect transistor (HFET) device, which includes sequentially forming a non-doped GaN semiconductor layer and an AlGaN semiconductor layer on a substrate, separating devices from each other by etching the substrate, forming a photoresist layer pattern on the AlGaN semiconductor layer and forming gate electrodes by depositing a material on the substrate using the photoresist layer pattern, treating the surface of the AlGaN semiconductor layer, and forming a photoresist layer pattern on the substrate and forming ohmic electrodes by depositing a metal on the substrate using the photoresist layer pattern, is provided. Accordingly, it is possible to overcome a difficulty in aligning the gate electrode with the ohmic electrodes and prevent a substrate from having a step difference introduced by the ohmic electrodes because the gate electrode is formed before the ohmic electrodes are formed.Type: GrantFiled: March 22, 2002Date of Patent: July 13, 2004Assignee: Pohang University of Science and Technology FoundationInventors: Jong-Lam Lee, Chang Min Jeon, Ho Won Jang
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Publication number: 20030190764Abstract: A gallium nitride (GaN) based optical device and a fabrication method thereof are provided. The GaN based optical device includes a substrate, a p-type GaN (p-GaN) layer formed on the substrate, and a p-type ohmic electrode formed on the p-GaN layer, wherein the p-type ohmic electrode is formed of a triple layer comprised of a nickel (Ni) layer, a gold (Au) layer and an indium tin oxide (ITO) layer sequentially formed. The thicknesses of the Ni layer and the Au layer forming the triple layer are smaller than the thickness of the ITO layer. When the p-type ohmic electrode in the GaN based optical device is formed of a triple layer comprised of Ni/Au/ITO, the Ni/Au layers reduce contact resistance and the ITO, which is a transparent, conductive oxide layer, increases transparency and increases luminescence efficiency.Type: ApplicationFiled: March 24, 2003Publication date: October 9, 2003Applicant: Pohang University of Science and Technology FoundationInventors: Jong Lam Lee, Soo Young Kim, Ho Won Jang
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Publication number: 20030189215Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.Type: ApplicationFiled: April 9, 2002Publication date: October 9, 2003Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Cheol Yoo
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Publication number: 20030183828Abstract: A p-type ohmic electrode in a gallium nitride based(GaN based) optical device and a fabrication method thereof. The p-type ohmic electrode in a GaN based optical device is fabricated using a rutile structure transition metal layer, such as an Ru, Ir or Os layer, or an oxide layer thereof, or using a double layer comprised of an Ru layer as a base layer and an Ni layer, an ITO layer or an AuO layer on the Ru layer. Thus, the p-type ohmic electrode is good in light transmittance and is thermally stable while having low contact resistance with the p-GaN layer.Type: ApplicationFiled: March 19, 2003Publication date: October 2, 2003Applicant: Pohang University of Science and Technology FoundationInventors: Jong Lam Lee, Ho Won Jang
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Publication number: 20030080347Abstract: A method for manufacturing a hetero-junction field effect transistor (HFET) device, which includes sequentially forming a non-doped GaN semiconductor layer and an AlGaN semiconductor layer on a substrate, separating devices from each other by etching the substrate, forming a photoresist layer pattern on the AlGaN semiconductor layer and forming gate electrodes by depositing a material on the substrate using the photoresist layer pattern, treating the surface of the AlGaN semiconductor layer, and forming a photoresist layer pattern on the substrate and forming ohmic electrodes by depositing a metal on the substrate using the photoresist layer pattern, is provided. Accordingly, it is possible to overcome a difficulty in aligning the gate electrode with the ohmic electrodes and prevent a substrate from having a step difference introduced by the ohmic electrodes because the gate electrode is formed before the ohmic electrodes are formed.Type: ApplicationFiled: March 22, 2002Publication date: May 1, 2003Applicant: Pohang University of Science and Technology FoundationInventors: Jong-Lam Lee, Chang Min Jeon, Ho Won Jang
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Publication number: 20020155691Abstract: Forming low contract resistance metal contacts on GaN films by treating a GaN surface using a chlorine gas Inductively Coupled Plasma (ICP) etch process before the metal contacts are formed. Beneficially, the GaN is n-type and doped with Si, while the metal contacts include alternating layers of Ti and Al. Additionally, the GaN film is dipped in a solution of HCl:H2O prior to metal contact formation.Type: ApplicationFiled: March 22, 2002Publication date: October 24, 2002Inventors: Jong Lam Lee, Ho Won Jang, Jong Kyu Kim, Changmin Jeon
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Patent number: 5760418Abstract: Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffer layer, a channel layer and a surface passivation layer on a semi-insulating GaAs substrate; etching a plurality of layers formed on the substrate using a device isolating mask so as to electrically isolate elements; selectively etching the surface passivation layer to form contact holes for source/drain formation and forming ohmic metallic layers in the contact holes; sequentially removing the surface passivation layer and the channel layer to some deep extent to form a contact hole for gate formation between the source and the drain; forming a gate in the contact hole and at the same time forming source and drain electrodes on the ohmic metallic layers; depositing a first SiN layer over the gate, the source and drain electrodes and the surface passivationType: GrantFiled: March 19, 1997Date of Patent: June 2, 1998Assignee: Electronics and Telecommunications Research InstituteInventors: Jong-Lam Lee, Hae-Cheon Kim, Jae-Kyoung Mun, Hyung-Moo Park
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Patent number: 5639677Abstract: Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffer layer, a channel layer and a surface passivation layer on a semi-insulating GaAs substrate; etching a plurality of layers formed on the substrate using a device isolating mask so as to electrically isolate elements; selectively etching the surface passivation layer to form contact holes for source/drain formation and forming ohmic metallic layers in the contact holes; sequentially removing the surface passivation layer and the channel layer to some deep extent to form a contact hole for gate formation between the source and the drain; forming a gate in the contact hole and at the same time forming source and drain electrodes on the ohmic metallic layers; depositing a first SiN layer over the gate, the source and drain electrodes and the surface passivationType: GrantFiled: June 19, 1996Date of Patent: June 17, 1997Assignee: Electronics and Telecommunications Research InstituteInventors: Jong-Lam Lee, Hae-Cheon Kim, Jae-Kyoung Mun, Hyung-Moo Park