Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Abstract: A semiconductor memory device includes a common driver suitable for generating a preliminary driving signal according to a voltage at a first node; and a plurality of individual drivers suitable for providing a core voltage to a sense amplifying circuit of a corresponding one of a plurality of cell mats, according to the preliminary driving signal, wherein each of the individual drivers includes: a level shifting circuit suitable for outputting a main driving signal by shifting a level of the preliminary driving signal when a corresponding mat select signal and a pull-up driving signal are activated; a pull-up driver suitable for driving a pull-up power line with the core voltage according to the main driving signal; and a switch suitable for coupling the first node to the pull-up power line when the corresponding mat select signal and the pull-up driving signal are activated.

Abstract: A semiconductor memory device includes a common driver suitable for generating a preliminary driving signal according to a voltage at a first node; and a plurality of individual drivers suitable for providing a core voltage to a sense amplifying circuit of a corresponding one of a plurality of cell mats, according to the preliminary driving signal, wherein each of the individual drivers includes: a level shifting circuit suitable for outputting a main driving signal by shifting a level of the preliminary driving signal when a corresponding mat select signal and a pull-up driving signal are activated; a pull-up driver suitable for driving a pull-up power line with the core voltage according to the main driving signal; and a switch suitable for coupling the first node to the pull-up power line when the corresponding mat select signal and the pull-up driving signal are activated.

Abstract: A semiconductor device includes a voltage adjust circuit suitable for generating an adjusting voltage according to a counting signal; an oscillating circuit operable by an oscillating control signal, and suitable for outputting an operational clock signal whose frequency is controlled by the adjusting voltage; a pumping circuit suitable for generating an internal voltage by pumping a source voltage according to the operational clock signal; and a counting circuit suitable for generating the counting signal by counting the operational clock signal according to the oscillating control signal.

Abstract: A semiconductor device includes a voltage adjust circuit suitable for generating an adjusting voltage according to a counting signal; an oscillating circuit operable by an oscillating control signal, and suitable for outputting an operational clock signal whose frequency is controlled by the adjusting voltage; a pumping circuit suitable for generating an internal voltage by pumping a source voltage according to the operational clock signal; and a counting circuit suitable for generating the counting signal by counting the operational clock signal according to the oscillating control signal.

Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Abstract: A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information. The controller generates a voltage control signal in response to the boot-up enable signal. The fuse latch array stores repair information provided from the fuse block. The voltage control signal, which is used as a bulk bias of a transistor formed in the fuse latch array, is adjustable.

Abstract: A semiconductor device includes: an internal voltage generation block suitable for generating an internal voltage based on first and second external voltages whose power-up sections are different from each other; and a control block suitable for fixing the internal voltage to a predetermined voltage level during a control section including a first power-up section of the first external voltage and a second power-up section of the second external voltage.

Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Abstract: A voltage generator may include: an internal voltage generation unit suitable for generating an internal voltage by pumping an external voltage in response to a pumping cycle signal; and a capacitance adjusting unit comprising a capacitive element which receives and transmits the pumping cycle signal to the internal voltage generation unit, and is suitable for adjusting a capacitance of the capacitive element based on the external voltage.

Abstract: A voltage generation circuit includes a plurality of voltage generation units each configured to include an internal voltage with a reference voltage, generate a detection signal based on a comparison result between the internal voltage and the reference voltage, and adjust the level of the internal voltage in response to an oscillation signal, a control unit configured to generate an oscillation control signal in response to the detection signals, an oscillator configured to generate the oscillation signal in response to the oscillation control signal, and a selective output unit configured to selectively supply the oscillation signal to one or more of the plurality of voltage generation units in response to the detection signals.

Abstract: A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information. The controller generates a voltage control signal in response to the boot-up enable signal. The fuse latch array stores repair information provided from the fuse block. The voltage control signal, which is used as a bulk bias of a transistor formed in the fuse latch array, is adjustable.

Abstract: A semiconductor device includes: an internal voltage generation block suitable for generating an internal voltage based on first and second external voltages whose power-up sections are different from each other; and a control block suitable for fixing the internal voltage to a predetermined voltage level during a control section including a first power-up section of the first external voltage and a second power-up section of the second external voltage.

Abstract: A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information. The controller generates a voltage control signal in response to the boot-up enable signal. The fuse latch array stores repair information provided from the fuse block. The voltage control signal, which is used as a bulk bias of a transistor formed in the fuse latch array, is adjustable.

Abstract: A voltage generation circuit includes a plurality of voltage generation units each configured to include an internal voltage with a reference voltage, generate a detection signal based on a comparison result between the internal voltage and the reference voltage, and adjust the level of the internal voltage in response to an oscillation signal, a control unit configured to generate an oscillation control signal in response to the detection signals, an oscillator configured to generate the oscillation signal in response to the oscillation control signal, and a selective output unit configured to selectively supply the oscillation signal to one or more of the plurality of voltage generation units in response to the detection signals.

Abstract: A semiconductor device includes: a sense amplification block suitable for sensing and amplifying a data loaded on a pair of data lines based on a pull-up driving voltage supplied through a pull-up power source line and a pull-down driving voltage supplied through a pull-down power source line; and a voltage supply block suitable for supplying a first high voltage as the pull-up driving voltage to the pull-up power source line and a first low voltage as the pull-down driving voltage to the pull-down power source line in a first mode, and supplying the first high voltage as the pull-up driving voltage to the pull-up power source line and a second low voltage having a voltage level lower than a voltage level of the first low voltage as the pull-down driving voltage to the pull-down power source line during an initial period of a second mode which is a subsequent mode of the first mode.

Abstract: A refresh control circuit of a semiconductor apparatus includes a variable delay unit configured to delay a signal that is activated quickest among a plurality of row address strobe signals activated at a predetermined time interval by a predetermined time, and to generate a preliminary pulse signal, and a piled delay unit configured to delay the preliminary pulse signal by various times, and to generate a plurality of refresh period pulse signals that are sequentially activated.

Abstract: A refresh control circuit of a semiconductor apparatus includes a variable delay unit configured to delay a signal that is activated quickest among a plurality of row address strobe signals activated at a predetermined time interval by a predetermined time, and to generate a preliminary pulse signal, and a piled delay unit configured to delay the preliminary pulse signal by various times, and to generate a plurality of refresh period pulse signals that are sequentially activated.

Abstract: A voltage generation circuit includes a plurality of voltage generation units each configured to include an internal voltage with a reference voltage, generate a detection signal based on a comparison result between the internal voltage and the reference voltage, and adjust the level of the internal voltage in response to an oscillation signal, a control unit configured to generate an oscillation control signal in response to the detection signals, an oscillator configured to generate the oscillation signal in response to the oscillation control signal, and a selective output unit configured to selectively supply the oscillation signal to one or more of the plurality of voltage generation units in response to the detection signals.