Patents by Inventor Jong Min JUNG

Jong Min JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9768106
    Abstract: A chip-on-film (COF) package includes a base film, a semiconductor chip mounted on a chip mounting region of a top surface of the base film, a plurality of top inner output conductive patterns, a plurality of bottom inner output conductive patterns and a plurality of landing vias. The top inner output conductive patterns are formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip. The bottom inner output conductive patterns are formed on a bottom surface of the base film. The landing vias are formed to vertically penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns. The landing vias are arranged within the chip mounting region to form a two-dimensional shape.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jin Cho, Jong-Min Jung, Yun-Ji Hur, Sung-Sik Park, Keun-Bong Lee
  • Publication number: 20160218053
    Abstract: A chip-on-film (COF) package includes a base film, a semiconductor chip mounted on a chip mounting region of a top surface of the base film, a plurality of top inner output conductive patterns, a plurality of bottom inner output conductive patterns and a plurality of landing vias. The top inner output conductive patterns are formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip. The bottom inner output conductive patterns are formed on a bottom surface of the base film. The landing vias are formed to vertically penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns. The landing vias are arranged within the chip mounting region to form a two-dimensional shape.
    Type: Application
    Filed: January 11, 2016
    Publication date: July 28, 2016
    Inventors: Young-Jin CHO, Jong-Min JUNG, Yun-Ji HUR, Sung-Sik PARK, Keun-Bong LEE
  • Publication number: 20080141338
    Abstract: A secure policy description method and apparatus for a secure operation system are provided. In the secure policy description method, a secure policy template is defined to have a subject, an object, and a permission assigned to the subject corresponding to the object. Then, the defined secure policy template is transformed to a TE (Type Enforcement) secure policy to be applied to a SELinux (Security enhanced Linux).
    Type: Application
    Filed: June 27, 2007
    Publication date: June 12, 2008
    Inventors: Dong Wook KIM, Kang Ho KIM, Baik Song AN, Sung In JUNG, Myung Joon KIM, Bong Nam NOH, Jung Sun KIM, Min Soo KIM, Jong Min JUNG