Abstract: A touch panel is provided. The touch panel includes a window, a sensor layer formed on a visible area of the window and comprising sensor patterns for detecting an input, a light shielding layer formed on a non-visible area of the window located around the sensor layer, wiring electrodes formed on the light shielding layer and connected to the sensor patterns such that the sensor layer is connected to an external connector, and etching masks formed on the wiring electrodes, respectively.

Abstract: A method for fabricating a touch panel, a touch panel, and an electronic device having the touch panel are provided. The touch panel includes a window member including a view area and a bezel area surrounding the view area, a sensor layer formed in the view area on a surface of the window member and including a sensor pattern for detecting a user input, a light blocking layer formed in the bezel area on the surface of the window member, a wiring layer formed on a surface of the light blocking layer and connected to the sensor pattern, and a barrier layer formed on the surface of the light blocking layer or a surface of the wiring layer.

Abstract: A method for fabricating a touch panel, a touch panel, and an electronic device having the touch panel are provided. The touch panel includes a window member including a view area and a bezel area surrounding the view area, a sensor layer formed in the view area on a surface of the window member and including a sensor pattern for detecting a user input, a light blocking layer formed in the bezel area on the surface of the window member, a wiring layer formed on a surface of the light blocking layer and connected to the sensor pattern, and a barrier layer formed on the surface of the light blocking layer or a surface of the wiring layer.

Abstract: A touch panel is provided. The touch panel includes a window, a sensor layer formed on a visible area of the window and comprising sensor patterns for detecting an input, a light shielding layer formed on a non-visible area of the window located around the sensor layer, wiring electrodes formed on the light shielding layer and connected to the sensor patterns such that the sensor layer is connected to an external connector, and etching masks formed on the wiring electrodes, respectively.

Abstract: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are included. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.

Abstract: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.

Abstract: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.

Abstract: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.

Abstract: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are included. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.

Abstract: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.

Abstract: A semiconductor memory device including a semiconductor substrate having a trench; a dielectric film formed on the substrate; a storage node electrode formed on the dielectric film; a first insulating film formed on the storage node electrode corresponding to the trench; a gate electrode formed on the first insulating film; a second insulating film formed on the gate electrode; a gate insulating film formed on at least one the side of gate electrode; a semiconductor layer formed on the at least one side of the first and second insulating films; and impurity regions formed in the semiconductor layer at the sides of the first and second insulating films.

Abstract: A semiconductor memory device including a semiconductor substrate having a trench; a dielectric film formed on the substrate; a storage node electrode formed on the dielectric film; a first insulating film formed on the storage node electrode corresponding to the trench; a gate electrode formed on the first insulating film; a second insulating film formed on the gate electrode; a gate insulating film formed on at least one the side of gate electrode; a semiconductor layer formed on the at least one side of the first and second insulating films; and impurity regions formed in the semiconductor layer at the sides of the first and second insulating films.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulation film formed on the substrate, a trench formed in the substrate, an opening formed in the first insulation film above the trench, a capacitor including a dielectric film formed in the trench and a storage node formed in the trench on the dielectric film, a transfer transistor including a channel layer formed in the opening on the storage node, a gate insulation film formed on the channel layer, and a gate electrode formed on the gate insulation film, a second insulation film formed on the gate electrode, a conduction layer formed on the second insulation film, a third insulation film in contact with the channel layer, and a bit line in contact with the conduction layer.