Patents by Inventor Jong-Phil Hong

Jong-Phil Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230280389
    Abstract: An insulation monitoring device, according to various embodiment of the present application, comprising an impedance formed between a power line and a ground of a system comprises, a signal generation circuit for applying a triangular wave signal to the power line through a signal measurement circuit, the signal measurement circuit for measuring a voltage difference across the detection resistor of the signal measurement circuit or a current flowing through the detection resistor when the triangular wave signal is applied to the impedance, a control circuit for obtaining an impedance value of the impedance based on at least one of the voltage difference and the current, and monitoring the impedance value.
    Type: Application
    Filed: September 7, 2020
    Publication date: September 7, 2023
    Applicants: DONGWOO ELECTRIC CORP., CHUNGBUK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Sun Woo Kim, Jong-Phil Hong
  • Patent number: 8847653
    Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Phil Hong, Jenlung Liu, Nan Xing, Jae Jin Park
  • Patent number: 8634511
    Abstract: A digital phase frequency detector includes a detection unit, a reset unit and a phase comparison unit. The detection unit detects edges of a reference signal and a feedback input signal to generate a reference edge signal and a feedback edge signal. The reset unit generates a reset signal resetting the detection unit based upon the reference edge signal and the feedback edge signal. The phase comparison unit generates first and second phase comparison signals based upon the reference edge signal and the feedback edge signal. The phase comparison unit includes a first flip-flop generating a first comparison signal based upon the reference edge signal and the feedback edge signal, a second flip-flop generating a second comparison signal based upon the reference edge signal and the feedback edge signal, and a latch block latching the first and second comparison signals to generate the first and second phase comparison signals.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: January 21, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Phil Hong, Ji-Hyun Kim, Jae-Jin Park
  • Publication number: 20120183104
    Abstract: A digital phase frequency detector includes a detection unit, a reset unit and a phase comparison unit. The detection unit detects edges of a reference signal and a feedback input signal to generate a reference edge signal and a feedback edge signal. The reset unit generates a reset signal resetting the detection unit based upon the reference edge signal and the feedback edge signal. The phase comparison unit generates first and second phase comparison signals based upon the reference edge signal and the feedback edge signal. The phase comparison unit includes a first flip-flop generating a first comparison signal based upon the reference edge signal and the feedback edge signal, a second flip-flop generating a second comparison signal based upon the reference edge signal and the feedback edge signal, and a latch block latching the first and second comparison signals to generate the first and second phase comparison signals.
    Type: Application
    Filed: December 9, 2011
    Publication date: July 19, 2012
    Inventors: JONG-PHIL HONG, Ji-Hyun Kim, Jae-Jin Park
  • Patent number: 8106718
    Abstract: A voltage controlled oscillator outputting a differential signal includes: an inductor connected to a first power supply supplying first voltage; first and second transistors for differential switching; first and second variable capacitors connected to the inductor in parallel; a third transistor of which a gate electrode is connected to a first node; and a fourth transistor of which a gate electrode is connected to a second node. When bias voltage is applied to the gate electrode of the first transistor to be turned on, negative resistance is generated by voltage applied to the first capacitor and the second capacitor through the first transistor. When voltage outputted through the first node is applied to the gate electrode of the third transistor to be turned on, the voltage is additionally applied to the first capacitor and the second capacitor by the third transistor to increase the negative resistance.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: January 31, 2012
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Sang-Gug Lee, Jong-Phil Hong
  • Publication number: 20100289592
    Abstract: A voltage controlled oscillator outputting a differential signal includes: an inductor connected to a first power supply supplying first voltage; first and second transistors for differential switching; first and second variable capacitors connected to the inductor in parallel; a third transistor of which a gate electrode is connected to a first node; and a fourth transistor of which a gate electrode is connected to a second node. When bias voltage is applied to the gate electrode of the first transistor to be turned on, negative resistance is generated by voltage applied to the first capacitor and the second capacitor through the first transistor. When voltage outputted through the first node is applied to the gate electrode of the third transistor to be turned on, the voltage is additionally applied to the first capacitor and the second capacitor by the third transistor to increase the negative resistance.
    Type: Application
    Filed: January 20, 2010
    Publication date: November 18, 2010
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Sang-Gug Lee, Jong-Phil Hong